Optimal code generation for embedded memory non-homogeneous register architectures

Guido Araujo; Sharad Malik

doi:10.1145/224486.224493

Optimal code generation for embedded memory non-homogeneous register architectures

Guido Araujo, Sharad Malik

Research output: Contribution to journal › Conference article › peer-review

43 Scopus citations

Abstract

This paper examines the problem of code-generation for expression trees on non-homogeneous register set architectures. It proposes and proves the optimality of an O(n) algorithm for the tasks of instruction selection, register allocation and scheduling on a class of architectures defined as the [1, ∞] Model. Optimality is guaranteed by sufficient conditions derived from the Register Transfer Graph (RTG), a structural representation of the architecture which depends exclusively on the processor Instruction Set Architecture (ISA). Experimental results using the TMS320C25 as the target processor show the efficacy of the approach.

Original language	English (US)
Pages (from-to)	36-41
Number of pages	6
Journal	Proceedings of the International Symposium on System Synthesis
DOIs	https://doi.org/10.1145/224486.224493
State	Published - 1995
Event	Proceedings of the 8th International Symposium on System Synthesis - Cannes, Fr Duration: Sep 13 1995 → Sep 15 1995

All Science Journal Classification (ASJC) codes

Hardware and Architecture

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10.1145/224486.224493

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abstract = "This paper examines the problem of code-generation for expression trees on non-homogeneous register set architectures. It proposes and proves the optimality of an O(n) algorithm for the tasks of instruction selection, register allocation and scheduling on a class of architectures defined as the [1, ∞] Model. Optimality is guaranteed by sufficient conditions derived from the Register Transfer Graph (RTG), a structural representation of the architecture which depends exclusively on the processor Instruction Set Architecture (ISA). Experimental results using the TMS320C25 as the target processor show the efficacy of the approach.",

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AU - Malik, Sharad

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N2 - This paper examines the problem of code-generation for expression trees on non-homogeneous register set architectures. It proposes and proves the optimality of an O(n) algorithm for the tasks of instruction selection, register allocation and scheduling on a class of architectures defined as the [1, ∞] Model. Optimality is guaranteed by sufficient conditions derived from the Register Transfer Graph (RTG), a structural representation of the architecture which depends exclusively on the processor Instruction Set Architecture (ISA). Experimental results using the TMS320C25 as the target processor show the efficacy of the approach.

AB - This paper examines the problem of code-generation for expression trees on non-homogeneous register set architectures. It proposes and proves the optimality of an O(n) algorithm for the tasks of instruction selection, register allocation and scheduling on a class of architectures defined as the [1, ∞] Model. Optimality is guaranteed by sufficient conditions derived from the Register Transfer Graph (RTG), a structural representation of the architecture which depends exclusively on the processor Instruction Set Architecture (ISA). Experimental results using the TMS320C25 as the target processor show the efficacy of the approach.

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T2 - Proceedings of the 8th International Symposium on System Synthesis

Y2 - 13 September 1995 through 15 September 1995

ER -

Optimal code generation for embedded memory non-homogeneous register architectures

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