Optimal code generation for embedded memory non-homogeneous register architectures

Guido Araujo, Sharad Malik

Research output: Contribution to journalArticlepeer-review

43 Scopus citations


This paper examines the problem of code-generation for expression trees on non-homogeneous register set architectures. It proposes and proves the optimality of an O(n) algorithm for the tasks of instruction selection, register allocation and scheduling on a class of architectures defined as the [1, ∞] Model. Optimality is guaranteed by sufficient conditions derived from the Register Transfer Graph (RTG), a structural representation of the architecture which depends exclusively on the processor Instruction Set Architecture (ISA). Experimental results using the TMS320C25 as the target processor show the efficacy of the approach.

Original languageEnglish (US)
Pages (from-to)36-41
Number of pages6
JournalProceedings of the International Symposium on System Synthesis
StatePublished - Dec 1 1995

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture


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