This paper examines the problem of code-generation for expression trees on non-homogeneous register set architectures. It proposes and proves the optimality of an O(n) algorithm for the tasks of instruction selection, register allocation and scheduling on a class of architectures defined as the [1, ∞] Model. Optimality is guaranteed by sufficient conditions derived from the Register Transfer Graph (RTG), a structural representation of the architecture which depends exclusively on the processor Instruction Set Architecture (ISA). Experimental results using the TMS320C25 as the target processor show the efficacy of the approach.
|Original language||English (US)|
|Number of pages||6|
|Journal||Proceedings of the International Symposium on System Synthesis|
|State||Published - Dec 1 1995|
All Science Journal Classification (ASJC) codes
- Hardware and Architecture