On the design of robust multiple fault testable CMOS combinational logic circuits

Sandip Kundu, Sudhakar M. Reddy, Niraj K. Jha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

27 Scopus citations

Abstract

Tests that detect modeled faults independent of the delays in the circuit under test are called robust tests. An integrated approach to the design of combinational logic circuits in which all single stuck-open faults and path delay faults are detectable by robust tests was presented by the authors earlier. It is shown here that the earlier design actually results in circuits in which all multiple stuck-at and stuck-open and multipath delay faults are robustly testable. The tests to detect such faults are presented.

Original languageEnglish (US)
Title of host publicationIEEE Int Conf on Comput Aided Des ICCAD 88 a Conf for the EE CAD Prof
PublisherPubl by IEEE
Pages240-243
Number of pages4
ISBN (Print)0818608692
StatePublished - Dec 1 1988
Externally publishedYes

Publication series

NameIEEE Int Conf on Comput Aided Des ICCAD 88 a Conf for the EE CAD Prof

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Fingerprint Dive into the research topics of 'On the design of robust multiple fault testable CMOS combinational logic circuits'. Together they form a unique fingerprint.

  • Cite this

    Kundu, S., Reddy, S. M., & Jha, N. K. (1988). On the design of robust multiple fault testable CMOS combinational logic circuits. In IEEE Int Conf on Comput Aided Des ICCAD 88 a Conf for the EE CAD Prof (pp. 240-243). (IEEE Int Conf on Comput Aided Des ICCAD 88 a Conf for the EE CAD Prof). Publ by IEEE.