In many scientific and signal processing applications, there are increasing demands for large-volume and/or high-speed computations which call for not only high-speed computing hardware, but also for novel approaches in computer architecture and software techniques in future supercomputers. Tremendous progress has been made on several promising parallel architectures for scientific computations, including a variety of digital filters, fast Fourier transform (FFT) processors, data-flow processors, systolic arrays, and wavefront arrays. This paper describes these computing networks in terms of signal-flow graphs (SFC) or data-flow graphs (DFC), and proposes a methodology of converting SFC computing networks into synchronous systolic arrays or data-driven wavefront arrays. Both one- and TwoDimensional arrays are discussed theoretically, as well as with illustrative examples. A wavefront-orientedprogramming language, which describes the (parallel) data flow in systolic/wavefront-type arrays, is presented. The structural property of parallel recursive algorithms points to the feasibility of a Hierarchical Iterative Flow-Graph Design (HIFD) of VLSI Array Processors. The proposed array processor architectures, we believe, will have significant impact on the development of future supercomputers.
|Original language||English (US)|
|Number of pages||18|
|Journal||Proceedings of the IEEE|
|State||Published - Jul 1984|
All Science Journal Classification (ASJC) codes
- Computer Science(all)
- Electrical and Electronic Engineering