Due to VLSI technological progress, algorithm-oriented array architectures appear to be most effective, feasible and economic. This trend necessitates a systematic methodology for mapping VLSI algorithms onto arrays. Some guidelines for achieving an optimal mapping are proposed. There will be three major stages in mapping algorithms onto arrays: (1) expressing an algorithm in terms of a (single assignment) dependence graph; (b) mapping the dependence graph onto an abstract SFG array; and (c) realization of systolic arrays by systolization. On the basis of the proposed methodology, systolic designs for the transitive closure problem are derived. The systolic array proposed here has the advantages of faster pipelining rates and fewer input/output connections over existing designs.
|Original language||English (US)|
|Number of pages||7|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|State||Published - Jan 1 1986|
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering