ON FAULT-TOLERANCE IN ARRAY PROCESSORS.

S. Y. Kung, D. D'Souza, J. T. Johl

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

A fault-tolerant model is developed for array processors. This model is used in analyzing the reliability of fully decoupled arrays. Other interconnection structures for constructing fault-tolerant arrays are investigated. It is found that the wavefront processing model offers advantages in achieving run-time tolerance.

Original languageEnglish (US)
Title of host publicationUnknown Host Publication Title
PublisherIEEE
Pages764-768
Number of pages5
ISBN (Print)0818606428
StatePublished - 1985
Externally publishedYes

All Science Journal Classification (ASJC) codes

  • General Engineering

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