On-chip lookup tables for fast symmetric-key encryption

A. Murat Fiskiran, Ruby B. Lee

Research output: Chapter in Book/Report/Conference proceedingConference contribution

33 Scopus citations

Abstract

On public communication networks such as the Internet, data confidentiality can be provided by symmetric-key ciphers. One of the most common operations used in symmetric-key ciphers are table lookups. These frequently constitute the largest fraction of the execution time when the ciphers are implemented using a typical RISC-like instruction set. To accelerate these table lookups, we describe a new hardware module, called PTLU (for Parallel Table Lookup), which consists of multiple lookup tables that can be accessed in parallel. A novel combinational circuit included in the module can optionally perform simple logic operations on the data read from the tables. On a single-issue 64-bit RISC processor, PTLU provides maximum speedups of 7.7× for AES and 5.4×. for DES. With wordsize scaling, PTLU speedups are significantly higher than that available through more conventional architectural techniques such as superscalar or VLIW execution.

Original languageEnglish (US)
Title of host publicationProceedings - 16th International Conference on Application-Specific Systems, Architectures, and Processors
Pages356-363
Number of pages8
DOIs
StatePublished - 2005
EventIEEE 16th International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2005 - Samos, Greece
Duration: Jul 23 2005Jul 25 2005

Publication series

NameProceedings of the International Conference on Application-Specific Systems, Architectures and Processors
ISSN (Print)1063-6862

Other

OtherIEEE 16th International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2005
CountryGreece
CitySamos
Period7/23/057/25/05

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Computer Networks and Communications

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