On-chip interconnection architecture of the tile processor

David Wentzlaff; Patrick Griffin; Henry Hoffmann; Liewei Bao; Bruce Edwards; Carl Ramey; Matthew Mattina; Chyi Chang Miao; John F. Brown; Anant Agarwal

doi:10.1109/MM.2007.4378780

On-chip interconnection architecture of the tile processor

David Wentzlaff
, Patrick Griffin
, Henry Hoffmann
, Liewei Bao
, Bruce Edwards
, Carl Ramey
, Matthew Mattina
, Chyi Chang Miao
, John F. Brown
, Anant Agarwal

Research output: Contribution to journal › Article › peer-review

694 Scopus citations

Abstract

iMesh, the Tile Processor Architecture's on-chip interconnection network, connects the multicore processor's tiles with five 2D mesh networks, each specialized for a different use. Taking advantage of the five networks, the c-based iLib interconnection library efficiently maps program communication across the on-chip interconnect. The Tile Processor's first implementation, the TILE64, contains 64 cores and can execute 192 billion 32-bit operations per second at 1 GHz.

Original language	English (US)
Pages (from-to)	15-31
Number of pages	17
Journal	IEEE Micro
Volume	27
Issue number	5
DOIs	https://doi.org/10.1109/MM.2007.4378780
State	Published - Sep 2007
Externally published	Yes

All Science Journal Classification (ASJC) codes

Software
Hardware and Architecture
Electrical and Electronic Engineering

Keywords

MIMD processors
Mesh networks
Multicore architectures
On chip interconnection
On-chip interconnection networks
Parallel architectures
Parallel processing
Tile processors

Access to Document

10.1109/MM.2007.4378780

Cite this

@article{f23221db67f34df09a51edc7b8979aec,

title = "On-chip interconnection architecture of the tile processor",

abstract = "iMesh, the Tile Processor Architecture's on-chip interconnection network, connects the multicore processor's tiles with five 2D mesh networks, each specialized for a different use. Taking advantage of the five networks, the c-based iLib interconnection library efficiently maps program communication across the on-chip interconnect. The Tile Processor's first implementation, the TILE64, contains 64 cores and can execute 192 billion 32-bit operations per second at 1 GHz.",

keywords = "MIMD processors, Mesh networks, Multicore architectures, On chip interconnection, On-chip interconnection networks, Parallel architectures, Parallel processing, Tile processors",

author = "David Wentzlaff and Patrick Griffin and Henry Hoffmann and Liewei Bao and Bruce Edwards and Carl Ramey and Matthew Mattina and Miao, \{Chyi Chang\} and Brown, \{John F.\} and Anant Agarwal",

year = "2007",

month = sep,

doi = "10.1109/MM.2007.4378780",

language = "English (US)",

volume = "27",

pages = "15--31",

journal = "IEEE Micro",

issn = "0272-1732",

publisher = "IEEE Computer Society",

number = "5",

}

TY - JOUR

T1 - On-chip interconnection architecture of the tile processor

AU - Wentzlaff, David

AU - Griffin, Patrick

AU - Hoffmann, Henry

AU - Bao, Liewei

AU - Edwards, Bruce

AU - Ramey, Carl

AU - Mattina, Matthew

AU - Miao, Chyi Chang

AU - Brown, John F.

AU - Agarwal, Anant

PY - 2007/9

Y1 - 2007/9

N2 - iMesh, the Tile Processor Architecture's on-chip interconnection network, connects the multicore processor's tiles with five 2D mesh networks, each specialized for a different use. Taking advantage of the five networks, the c-based iLib interconnection library efficiently maps program communication across the on-chip interconnect. The Tile Processor's first implementation, the TILE64, contains 64 cores and can execute 192 billion 32-bit operations per second at 1 GHz.

AB - iMesh, the Tile Processor Architecture's on-chip interconnection network, connects the multicore processor's tiles with five 2D mesh networks, each specialized for a different use. Taking advantage of the five networks, the c-based iLib interconnection library efficiently maps program communication across the on-chip interconnect. The Tile Processor's first implementation, the TILE64, contains 64 cores and can execute 192 billion 32-bit operations per second at 1 GHz.

KW - MIMD processors

KW - Mesh networks

KW - Multicore architectures

KW - On chip interconnection

KW - On-chip interconnection networks

KW - Parallel architectures

KW - Parallel processing

KW - Tile processors

UR - https://www.scopus.com/pages/publications/36849030305

UR - https://www.scopus.com/pages/publications/36849030305#tab=citedBy

U2 - 10.1109/MM.2007.4378780

DO - 10.1109/MM.2007.4378780

M3 - Article

AN - SCOPUS:36849030305

SN - 0272-1732

VL - 27

SP - 15

EP - 31

JO - IEEE Micro

JF - IEEE Micro

IS - 5

ER -

On-chip interconnection architecture of the tile processor

Abstract

All Science Journal Classification (ASJC) codes

Keywords

Access to Document

Other files and links

Fingerprint

Cite this