On-chip interconnection architecture of the tile processor

David Wentzlaff, Patrick Griffin, Henry Hoffmann, Liewei Bao, Bruce Edwards, Carl Ramey, Matthew Mattina, Chyi Chang Miao, John F. Brown, Anant Agarwal

Research output: Contribution to journalArticle

565 Scopus citations

Abstract

iMesh, the Tile Processor Architecture's on-chip interconnection network, connects the multicore processor's tiles with five 2D mesh networks, each specialized for a different use. Taking advantage of the five networks, the c-based iLib interconnection library efficiently maps program communication across the on-chip interconnect. The Tile Processor's first implementation, the TILE64, contains 64 cores and can execute 192 billion 32-bit operations per second at 1 GHz.

Original languageEnglish (US)
Pages (from-to)15-31
Number of pages17
JournalIEEE Micro
Volume27
Issue number5
DOIs
StatePublished - Sep 2007
Externally publishedYes

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Keywords

  • MIMD processors
  • Mesh networks
  • Multicore architectures
  • On chip interconnection
  • On-chip interconnection networks
  • Parallel architectures
  • Parallel processing
  • Tile processors

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  • Cite this

    Wentzlaff, D., Griffin, P., Hoffmann, H., Bao, L., Edwards, B., Ramey, C., Mattina, M., Miao, C. C., Brown, J. F., & Agarwal, A. (2007). On-chip interconnection architecture of the tile processor. IEEE Micro, 27(5), 15-31. https://doi.org/10.1109/MM.2007.4378780