Networks of the Tilera Multicore Processor

David Wentzlaff, Patrick Griffin, Henry Hoffmann, Liewei Bao, Bruce Edwards, Carl Ramey, Matthew Mattina, Chyi Chang Miao, John F. Brown, Anant Agarwal

Research output: Chapter in Book/Report/Conference proceedingChapter


As a greater number of processor cores is integrated onto a single die, the design space for interconnecting these cores becomes more fertile. One manner to interconnect those cores is simply to mimic multichip multiprocessor computers of the past. Following the past, simple bus-based shared memory multiprocessors can be integrated onto a single piece of silicon. But, by following the past, we do not take advantage of the unique opportunities afforded by single-chip integration. Specifically, buses require global broadcast and do not scale to more than about 8 or 16 cores. Some multicore processors have used one-dimensional rings, but rings do not scale either because their bisection bandwidth does not increase as more cores as added.

Original languageEnglish (US)
Title of host publicationDesigning Network On-Chip Architectures in the Nanoscale Era
PublisherCRC Press
Number of pages25
ISBN (Electronic)9781439837115
ISBN (Print)9781439837108
StatePublished - Jan 1 2010
Externally publishedYes

All Science Journal Classification (ASJC) codes

  • General Computer Science
  • General Engineering


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