Abstract
The fault-tolerance issue for arrays of large numbers of processors is considered. An array grid model based on single-track switches is adopted. Single track requires less hardware overhead and suffers less from possible faults on switches. More significantly, it is possible to establish a very critical necessary and sufficient condition for the reconfigurability of such an array. This is used as the theoretical footing for the reconfiguration algorithm, using global control, for the (fabrication-time) yield enhancement. This approach can also effectively deal with failures of switches), wires, and connections to obtain a solution. The simulations conducted indicate that a significant yield enhancement can be achieved.
| Original language | English (US) |
|---|---|
| Title of host publication | Proc Int Conf Wafer Scale Integr |
| Editors | Earl Swartzlander, Joe Brewer |
| Publisher | Publ by IEEE |
| Pages | 401-412 |
| Number of pages | 12 |
| ISBN (Print) | 0818699019 |
| State | Published - Dec 1 1989 |
| Event | Proceedings: International Conference on Wafer Scale Integration - San Francisco, CA, USA Duration: Jan 3 1989 → Jan 5 1989 |
Other
| Other | Proceedings: International Conference on Wafer Scale Integration |
|---|---|
| City | San Francisco, CA, USA |
| Period | 1/3/89 → 1/5/89 |
All Science Journal Classification (ASJC) codes
- Engineering(all)