NATURE: A hybrid nanotube/CMOS dynamically reconfigurable architecture

Wei Zhang, Niraj K. Jha, Li Shang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

28 Scopus citations


Recent progress on nanodevices, such as carbon nanotubes and nanowires, points to promising directions for future circuit design. However, nanofabrication techniques are not yet mature, making implementation of such circuits, at least on a large scale, in the near future infeasible. However, if photo-lithography could be used to implement circuits using these nanodevices, then hybrid nano/CMOS chips could be fabricated and the benefits of nanotechnology could be utilized immediately. A startup company, called Nantero, has developed and implemented a non-volatile nanotube random-access memory (NRAM) using photo-lithography that is considerably faster and denser than DRAM, has much lower power consumption than DRAM or flash, has similar speed to SRAM and is highly resistant to environmental forces (temperature, magnetism). In this paper, we propose a novel high performance reconfigurable architecture, called NATURE, that utilizes CMOS logic and NRAMs. Use of the highly-dense NRAMs allows large on-chip configuration storage, enabling fine-grain run-time reconfiguration and temporal logic folding of a circuit before being mapped to the architecture. This can significantly increase the logic density of NATURE (by over an order of magnitude for larger circuits) while remaining competitive in performance. Compared to traditional reconfigurable architectures, NATURE also allows the designer the flexibility to adjust the level of logic folding in order to improve performance or perform area-performance trade-offs. Experimental results establish its efficacy and give comparisons with today's mainstream FPGA technology which does not allow logic folding.

Original languageEnglish (US)
Title of host publication2006 43rd ACM/IEEE Design Automation Conference, DAC'06
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages6
ISBN (Print)1595933816, 1595933816, 9781595933812
StatePublished - 2006
Event43rd Annual Design Automation Conference, DAC 2006 - San Francisco, CA, United States
Duration: Jul 24 2006Jul 28 2006

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X


Conference43rd Annual Design Automation Conference, DAC 2006
Country/TerritoryUnited States
CitySan Francisco, CA

All Science Journal Classification (ASJC) codes

  • Control and Systems Engineering
  • Hardware and Architecture


  • Logic folding
  • NRAM
  • Run-time reconfiguration


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