NanoV: Nanowire-based VLSI design

Muzaffer O. Simsir, Niraj K. Jha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

In the coming decade, CMOS technology is expected to approach its scaling limitations. Among the proposed nanotechnologies, nanowires have the edge in the size of circuits and logic arrays that have already been fabricated and experimentally evaluated. For this technology, logic-level design methodologies are being developed. The time has now come to develop automated tools for implementing VLSI designs using nanowires. In this paper, we discuss a design automation tool, called NanoV, to fulfill this need for nanowires. It is a complete logic-to-layout tool with built-in defect-aware steps since the defect levels in nanotechnologies are expected to be relatively high (between 1 to 10%). We are unaware of any other such comprehensive VLSI design tool for nanowires. We report area/delay/power results for various benchmarks implemented using our tool. We intend to make the tool available on the web.

Original languageEnglish (US)
Title of host publicationProceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010
Pages53-58
Number of pages6
DOIs
StatePublished - Aug 24 2010
Event2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010 - Anaheim, CA, United States
Duration: Jun 17 2010Jun 18 2010

Publication series

NameProceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010

Other

Other2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010
CountryUnited States
CityAnaheim, CA
Period6/17/106/18/10

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Keywords

  • Computer-aided design
  • Nanowire
  • Physical design
  • Synthesis

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