NanoV: Nanowire-based VLSI design

Muzaffer O. Simsir; Niraj K. Jha

doi:10.1109/NANOARCH.2010.5510925

NanoV: Nanowire-based VLSI design

Muzaffer O. Simsir, Niraj K. Jha

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Scopus citations

Abstract

In the coming decade, CMOS technology is expected to approach its scaling limitations. Among the proposed nanotechnologies, nanowires have the edge in the size of circuits and logic arrays that have already been fabricated and experimentally evaluated. For this technology, logic-level design methodologies are being developed. The time has now come to develop automated tools for implementing VLSI designs using nanowires. In this paper, we discuss a design automation tool, called NanoV, to fulfill this need for nanowires. It is a complete logic-to-layout tool with built-in defect-aware steps since the defect levels in nanotechnologies are expected to be relatively high (between 1 to 10%). We are unaware of any other such comprehensive VLSI design tool for nanowires. We report area/delay/power results for various benchmarks implemented using our tool. We intend to make the tool available on the web.

Original language	English (US)
Title of host publication	Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010
Pages	53-58
Number of pages	6
DOIs	https://doi.org/10.1109/NANOARCH.2010.5510925
State	Published - 2010
Event	2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010 - Anaheim, CA, United States Duration: Jun 17 2010 → Jun 18 2010

Publication series

Name	Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010

Other

Other	2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010
Country/Territory	United States
City	Anaheim, CA
Period	6/17/10 → 6/18/10

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Keywords

Computer-aided design
Nanowire
Physical design
Synthesis

Access to Document

10.1109/NANOARCH.2010.5510925

Cite this

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title = "NanoV: Nanowire-based VLSI design",

abstract = "In the coming decade, CMOS technology is expected to approach its scaling limitations. Among the proposed nanotechnologies, nanowires have the edge in the size of circuits and logic arrays that have already been fabricated and experimentally evaluated. For this technology, logic-level design methodologies are being developed. The time has now come to develop automated tools for implementing VLSI designs using nanowires. In this paper, we discuss a design automation tool, called NanoV, to fulfill this need for nanowires. It is a complete logic-to-layout tool with built-in defect-aware steps since the defect levels in nanotechnologies are expected to be relatively high (between 1 to 10%). We are unaware of any other such comprehensive VLSI design tool for nanowires. We report area/delay/power results for various benchmarks implemented using our tool. We intend to make the tool available on the web.",

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author = "Simsir, {Muzaffer O.} and Jha, {Niraj K.}",

year = "2010",

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isbn = "9781424480180",

series = "Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010",

pages = "53--58",

booktitle = "Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010",

note = "2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010 ; Conference date: 17-06-2010 Through 18-06-2010",

}

Simsir, MO & Jha, NK 2010, NanoV: Nanowire-based VLSI design. in Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010., 5510925, Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010, pp. 53-58, 2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010, Anaheim, CA, United States, 6/17/10. https://doi.org/10.1109/NANOARCH.2010.5510925

NanoV: Nanowire-based VLSI design. / Simsir, Muzaffer O.; Jha, Niraj K.
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010. 2010. p. 53-58 5510925 (Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AB - In the coming decade, CMOS technology is expected to approach its scaling limitations. Among the proposed nanotechnologies, nanowires have the edge in the size of circuits and logic arrays that have already been fabricated and experimentally evaluated. For this technology, logic-level design methodologies are being developed. The time has now come to develop automated tools for implementing VLSI designs using nanowires. In this paper, we discuss a design automation tool, called NanoV, to fulfill this need for nanowires. It is a complete logic-to-layout tool with built-in defect-aware steps since the defect levels in nanotechnologies are expected to be relatively high (between 1 to 10%). We are unaware of any other such comprehensive VLSI design tool for nanowires. We report area/delay/power results for various benchmarks implemented using our tool. We intend to make the tool available on the web.

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NanoV: Nanowire-based VLSI design

Abstract

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All Science Journal Classification (ASJC) codes

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