Nanometer MOSFET variation in minimum energy subthreshold circuits

Naveen Verma; Joyce Kwong; Anantha P. Chandrakasan

doi:10.1109/TED.2007.911352

Nanometer MOSFET variation in minimum energy subthreshold circuits

Naveen Verma, Joyce Kwong, Anantha P. Chandrakasan

Research output: Contribution to journal › Article › peer-review

138 Scopus citations

Abstract

Minimum energy operation for digital circuits typically requires scaling the power supply below the device threshold voltage. Advanced technologies offer improved integration, performance, and active-energy efficiency for minimum energy sub-V_t circuits, but are plagued by increased variation and reduced I_ON/I_OFF ratios, which degrade the fundamental device characteristics critical to circuit operation by several orders of magnitude. This paper investigates those characteristics and presents design methodologies and circuit topologies to manage their severe degradation. The issues specific to both general logic and dense static random access memories are analyzed, and solutions that address their distinct design metrics are presented.

Original language	English (US)
Pages (from-to)	163-174
Number of pages	12
Journal	IEEE Transactions on Electron Devices
Volume	55
Issue number	1
DOIs	https://doi.org/10.1109/TED.2007.911352
State	Published - Jan 2008
Externally published	Yes

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Keywords

CMOS digital integrated circuits
Leakage currents
Logic design
Low-power electronics
Matching
Static random access memory (SRAM)
Subthreshold
Yield estimation

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10.1109/TED.2007.911352

Cite this

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title = "Nanometer MOSFET variation in minimum energy subthreshold circuits",

abstract = "Minimum energy operation for digital circuits typically requires scaling the power supply below the device threshold voltage. Advanced technologies offer improved integration, performance, and active-energy efficiency for minimum energy sub-Vt circuits, but are plagued by increased variation and reduced ION/IOFF ratios, which degrade the fundamental device characteristics critical to circuit operation by several orders of magnitude. This paper investigates those characteristics and presents design methodologies and circuit topologies to manage their severe degradation. The issues specific to both general logic and dense static random access memories are analyzed, and solutions that address their distinct design metrics are presented.",

keywords = "CMOS digital integrated circuits, Leakage currents, Logic design, Low-power electronics, Matching, Static random access memory (SRAM), Subthreshold, Yield estimation",

author = "Naveen Verma and Joyce Kwong and Chandrakasan, {Anantha P.}",

note = "Funding Information: He is the recipient of the Intel Foundation Ph.D. fellowship and the NSERC Postgraduate fellowship. His research interests include low-power mixed signal circuits in the areas of analog-to-digital converters, SRAMs, and implantable biological systems. Funding Information: Manuscript received May 29, 2007. This work was supported by the Defense Advanced Research Projects Agency. The work of N. Verma was supported by the Intel Foundation Ph.D. Fellowship Program and NSERC. The review of this paper was arranged by Editor S. Kosonocky. Funding Information: She is the recipient of the Texas Instruments Graduate Woman{\textquoteright}s Fellowship for Leadership in Microelectronics and the NSERC Postgraduate Fellowship. Her research interests include subthreshold circuit design methodology and system implementation.",

year = "2008",

month = jan,

doi = "10.1109/TED.2007.911352",

language = "English (US)",

volume = "55",

pages = "163--174",

journal = "IEEE Transactions on Electron Devices",

issn = "0018-9383",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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AU - Verma, Naveen

AU - Kwong, Joyce

AU - Chandrakasan, Anantha P.

N1 - Funding Information: He is the recipient of the Intel Foundation Ph.D. fellowship and the NSERC Postgraduate fellowship. His research interests include low-power mixed signal circuits in the areas of analog-to-digital converters, SRAMs, and implantable biological systems. Funding Information: Manuscript received May 29, 2007. This work was supported by the Defense Advanced Research Projects Agency. The work of N. Verma was supported by the Intel Foundation Ph.D. Fellowship Program and NSERC. The review of this paper was arranged by Editor S. Kosonocky. Funding Information: She is the recipient of the Texas Instruments Graduate Woman’s Fellowship for Leadership in Microelectronics and the NSERC Postgraduate Fellowship. Her research interests include subthreshold circuit design methodology and system implementation.

PY - 2008/1

Y1 - 2008/1

N2 - Minimum energy operation for digital circuits typically requires scaling the power supply below the device threshold voltage. Advanced technologies offer improved integration, performance, and active-energy efficiency for minimum energy sub-Vt circuits, but are plagued by increased variation and reduced ION/IOFF ratios, which degrade the fundamental device characteristics critical to circuit operation by several orders of magnitude. This paper investigates those characteristics and presents design methodologies and circuit topologies to manage their severe degradation. The issues specific to both general logic and dense static random access memories are analyzed, and solutions that address their distinct design metrics are presented.

AB - Minimum energy operation for digital circuits typically requires scaling the power supply below the device threshold voltage. Advanced technologies offer improved integration, performance, and active-energy efficiency for minimum energy sub-Vt circuits, but are plagued by increased variation and reduced ION/IOFF ratios, which degrade the fundamental device characteristics critical to circuit operation by several orders of magnitude. This paper investigates those characteristics and presents design methodologies and circuit topologies to manage their severe degradation. The issues specific to both general logic and dense static random access memories are analyzed, and solutions that address their distinct design metrics are presented.

KW - CMOS digital integrated circuits

KW - Leakage currents

KW - Logic design

KW - Low-power electronics

KW - Matching

KW - Static random access memory (SRAM)

KW - Subthreshold

KW - Yield estimation

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Nanometer MOSFET variation in minimum energy subthreshold circuits

Abstract

All Science Journal Classification (ASJC) codes

Keywords

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