Nanometer MOSFET variation in minimum energy subthreshold circuits

Naveen Verma, Joyce Kwong, Anantha P. Chandrakasan

Research output: Contribution to journalArticle

124 Scopus citations

Abstract

Minimum energy operation for digital circuits typically requires scaling the power supply below the device threshold voltage. Advanced technologies offer improved integration, performance, and active-energy efficiency for minimum energy sub-Vt circuits, but are plagued by increased variation and reduced ION/IOFF ratios, which degrade the fundamental device characteristics critical to circuit operation by several orders of magnitude. This paper investigates those characteristics and presents design methodologies and circuit topologies to manage their severe degradation. The issues specific to both general logic and dense static random access memories are analyzed, and solutions that address their distinct design metrics are presented.

Original languageEnglish (US)
Pages (from-to)163-174
Number of pages12
JournalIEEE Transactions on Electron Devices
Volume55
Issue number1
DOIs
StatePublished - Jan 1 2008
Externally publishedYes

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Keywords

  • CMOS digital integrated circuits
  • Leakage currents
  • Logic design
  • Low-power electronics
  • Matching
  • Static random access memory (SRAM)
  • Subthreshold
  • Yield estimation

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