Nano-graphoepitaxy of semiconductors for 3D integration

F. Crnogorac, D. J. Witte, Q. Xia, B. Rajendran, D. S. Pickard, Z. Liu, A. Mehta, S. Sharma, A. Yasseri, T. I. Kamins, S. Y. Chou, R. F.W. Pease

Research output: Contribution to journalArticlepeer-review

10 Scopus citations


The advantages of integrating semiconductor devices at more than one level ('3D integration') are now recognized. Key to achieving monolithic 3DICs is the ability to form single crystal semiconductor islands at the upper level without unduly heating the lower level structures. In prior work a surface relief grating of 3.8 μm pitch in the substrate was used to mediate single crystal formation while continuous wave (CW) heating a thin film of amorphous silicon; the term 'graphoepitaxy' was coined. CW heating is not possible in our case because it would overheat the lower layers. Moreover the area of the crystallites need only be about 100 nm to accommodate today's transistors. Thus we have chosen a substrate grating pitch of 190 nm (hence the term 'nano-graphoepitaxy') and a modulated CW laser to reduce the heating time to several μs. Preliminary results indicate the substrate grating lines can indeed determine the position of the crystallite boundaries when the film thickness is 100 nm; the effect is much less pronounced in 500 nm thick films.

Original languageEnglish (US)
Pages (from-to)891-894
Number of pages4
JournalMicroelectronic Engineering
Issue number5-8
StatePublished - May 2007

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Atomic and Molecular Physics, and Optics
  • Condensed Matter Physics
  • Surfaces, Coatings and Films
  • Electrical and Electronic Engineering


  • Crystallization
  • Graphoepitaxy
  • Nanoimprint
  • Transient heating


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