TY - JOUR
T1 - Multitrack Power Factor Correction Architecture
AU - Chen, Minjie
AU - Chakraborty, Sombuddha
AU - Perreault, David J.
N1 - Funding Information:
Manuscript received April 3, 2018; revised May 22, 2018; accepted June 7, 2018. Date of publication June 13, 2018; date of current version February 5, 2019. This work was supported in part by the Texas Instruments, the Center for Integrated Circuits and Systems, Massachusetts Institute of Technology, in part by the the Andlinger Center for Energy and the Environment, Princeton University, and in part by the Siebel Energy Institute. Recommended for publication by Associate Editor R. Redl. (Corresponding author: Minjie Chen.) M. Chen is with the Department of Electrical Engineering and with the An-dlinger Center for Energy and the Environment, Princeton University, Princeton, NJ 08540 USA (e-mail:,minjie@princeton.edu).
Publisher Copyright:
© 1986-2012 IEEE.
PY - 2019/3
Y1 - 2019/3
N2 - Single-phase universal-input ac-dc converters are needed in a wide range of applications. This paper presents a novel power factor correction (PFC) architecture that can achieve high-power density and high efficiency for grid-interface power electronics. The multitrack PFC architecture reduces the internal device voltage stress of the power converter subsystems, allowing PFC circuits to maintain zero-voltage-switching at high frequency (1 MHz-4 MHz) across universal input voltage range (85 V ac-265 V ac). The high performance of the power converter is enabled by delivering power in multiple stacked voltage domains and reconfiguring the power processing paths depending on the input voltage. This multitrack concept can be used together with many other design techniques for PFC systems to create mutual advantages in many function blocks. A prototype 150 W, universal ac input, 12 V dc output, isolated multitrack PFC system with a power density of 50 W/in3, and a peak end-to-end efficiency of 92% has been built and tested to verify the effectiveness of the multitrack PFC architecture.
AB - Single-phase universal-input ac-dc converters are needed in a wide range of applications. This paper presents a novel power factor correction (PFC) architecture that can achieve high-power density and high efficiency for grid-interface power electronics. The multitrack PFC architecture reduces the internal device voltage stress of the power converter subsystems, allowing PFC circuits to maintain zero-voltage-switching at high frequency (1 MHz-4 MHz) across universal input voltage range (85 V ac-265 V ac). The high performance of the power converter is enabled by delivering power in multiple stacked voltage domains and reconfiguring the power processing paths depending on the input voltage. This multitrack concept can be used together with many other design techniques for PFC systems to create mutual advantages in many function blocks. A prototype 150 W, universal ac input, 12 V dc output, isolated multitrack PFC system with a power density of 50 W/in3, and a peak end-to-end efficiency of 92% has been built and tested to verify the effectiveness of the multitrack PFC architecture.
KW - AC-DC power conversion
KW - grid-tied power electronics
KW - multitrack architecture
KW - power factor correction (PFC)
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U2 - 10.1109/TPEL.2018.2847284
DO - 10.1109/TPEL.2018.2847284
M3 - Article
AN - SCOPUS:85048566306
SN - 0885-8993
VL - 34
SP - 2454
EP - 2466
JO - IEEE Transactions on Power Electronics
JF - IEEE Transactions on Power Electronics
IS - 3
M1 - 8385184
ER -