Multitrack power factor correction architecture

Minjie Chen, Sombuddha Chakraborty, David J. Perreault

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

Single-phase universal-input ac-dc converters are needed in a wide range of applications. This paper presents a novel power factor correction (PFC) architecture that can achieve high power density and high efficiency as a new development of the Multitrack concept [1]. The proposed Multitrack PFC architecture reduces the internal device voltage stress of the power converter subsystems, allowing PFC circuits to maintain zero-voltage-switching (ZVS) at high frequencies (HF, 1-3 MHz) across universal input voltage range (85Vac-265Vac) and wide power range. The high performance of the power converter is enabled by delivering power in multiple stacked voltage domains and reconfiguring the power processing paths depending on the input voltage. This Multitrack concept is compatible with a wide range of existing design techniques for PFC systems. A prototype 150W, universal ac input, 12VDC output, isolated Multitrack PFC system with a power density of 50W/inch3 and a peak end-to-end efficiency of 92% has been built and tested to verify the effectiveness of the Multitrack PFC architecture.

Original languageEnglish (US)
Title of host publicationAPEC 2018 - 33rd Annual IEEE Applied Power Electronics Conference and Exposition
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages737-745
Number of pages9
ISBN (Electronic)9781538611807
DOIs
StatePublished - Apr 18 2018
Event33rd Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2018 - San Antonio, United States
Duration: Mar 4 2018Mar 8 2018

Publication series

NameConference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC
Volume2018-March

Other

Other33rd Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2018
CountryUnited States
CitySan Antonio
Period3/4/183/8/18

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Multitrack power factor correction architecture'. Together they form a unique fingerprint.

Cite this