TY - GEN
T1 - Multitrack power factor correction architecture
AU - Chen, Minjie
AU - Chakraborty, Sombuddha
AU - Perreault, David J.
N1 - Publisher Copyright:
© 2018 IEEE.
PY - 2018/4/18
Y1 - 2018/4/18
N2 - Single-phase universal-input ac-dc converters are needed in a wide range of applications. This paper presents a novel power factor correction (PFC) architecture that can achieve high power density and high efficiency as a new development of the Multitrack concept [1]. The proposed Multitrack PFC architecture reduces the internal device voltage stress of the power converter subsystems, allowing PFC circuits to maintain zero-voltage-switching (ZVS) at high frequencies (HF, 1-3 MHz) across universal input voltage range (85Vac-265Vac) and wide power range. The high performance of the power converter is enabled by delivering power in multiple stacked voltage domains and reconfiguring the power processing paths depending on the input voltage. This Multitrack concept is compatible with a wide range of existing design techniques for PFC systems. A prototype 150W, universal ac input, 12VDC output, isolated Multitrack PFC system with a power density of 50W/inch3 and a peak end-to-end efficiency of 92% has been built and tested to verify the effectiveness of the Multitrack PFC architecture.
AB - Single-phase universal-input ac-dc converters are needed in a wide range of applications. This paper presents a novel power factor correction (PFC) architecture that can achieve high power density and high efficiency as a new development of the Multitrack concept [1]. The proposed Multitrack PFC architecture reduces the internal device voltage stress of the power converter subsystems, allowing PFC circuits to maintain zero-voltage-switching (ZVS) at high frequencies (HF, 1-3 MHz) across universal input voltage range (85Vac-265Vac) and wide power range. The high performance of the power converter is enabled by delivering power in multiple stacked voltage domains and reconfiguring the power processing paths depending on the input voltage. This Multitrack concept is compatible with a wide range of existing design techniques for PFC systems. A prototype 150W, universal ac input, 12VDC output, isolated Multitrack PFC system with a power density of 50W/inch3 and a peak end-to-end efficiency of 92% has been built and tested to verify the effectiveness of the Multitrack PFC architecture.
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U2 - 10.1109/APEC.2018.8341094
DO - 10.1109/APEC.2018.8341094
M3 - Conference contribution
AN - SCOPUS:85046957924
T3 - Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC
SP - 737
EP - 745
BT - APEC 2018 - 33rd Annual IEEE Applied Power Electronics Conference and Exposition
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 33rd Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2018
Y2 - 4 March 2018 through 8 March 2018
ER -