Multiprocessor main memory transaction processing

Kai Li, Jeffrey F. Naughton

Research output: Chapter in Book/Report/Conference proceedingConference contribution

28 Scopus citations


A description is given of an experiment designed to evaluate the potential transaction-processing-system performance achievable through the combination of multiple processors and massive memories. The experiment consisted of the design and implementation of a transaction-processing kernel on stock multiprocessors. The authors found that with sufficient memory, multiple processors can greatly improve performance. A prototoype implementation of the kernel on a pair of Firefly multiprocessors (each with five 1-MIP processors) runs the standard debit-credit benchmark at over 1000 transactions per second.

Original languageEnglish (US)
Title of host publicationProc Int Symp on Databases in Parallel Distrib Syst
EditorsSushil Jajodia, Won Kim, Abraham Silberschatz
PublisherPubl by IEEE
Number of pages11
ISBN (Print)0818608935
StatePublished - 1988

Publication series

NameProc Int Symp on Databases in Parallel Distrib Syst

All Science Journal Classification (ASJC) codes

  • General Engineering


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