We discuss the integer and floating-point multimedia instructions in the IA-64 instruction-set architecture (ISA). These multimedia instructions implement subword parallelism, also called packed parallelism or microSIMD parallelism. They are both a subset and a superset of the multimedia instructions from the predecessor architectures: MMX, SSE and SSE-2 from the IA-32 architecture, and MAX and MAX-2 from the PARISC architecture. We discuss the novel subword permutation instructions that are new in the IA-64, and their effectiveness, in combination with the subword arithmetic instructions, for speeding up multimedia programs. These packed arithmetic and permutation instructions can also be used in media processors and DSPs for very fast and cost-effective multimedia processing.
|Original language||English (US)|
|Number of pages||4|
|Journal||Proceedings - IEEE International Conference on Multimedia and Expo|
|State||Published - Jan 1 2001|
All Science Journal Classification (ASJC) codes
- Computer Networks and Communications
- Computer Science Applications