MRPB: Memory request prioritization for massively parallel processors

Wenhao Jia, Kelly A. Shaw, Margaret Rose Martonosi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

108 Scopus citations

Abstract

Massively parallel, throughput-oriented systems such as graphics processing units (GPUs) offer high performance for a broad range of programs. They are, however, complex to program, especially because of their intricate memory hierarchies with multiple address spaces. In response, modern GPUs have widely adopted caches, hoping to providing smoother reductions in memory access traffic and latency. Unfortunately, GPU caches often have mixed or unpredictable performance impact due to cache contention that results from the high thread counts in GPUs. We propose the memory request prioritization buffer (MRPB) to ease GPU programming and improve GPU performance. This hardware structure improves caching efficiency of massively parallel workloads by applying two prioritization methods - request reordering and cache bypassing - to memory requests before they access a cache. MRPB then releases requests into the cache in a more cache-friendly order. The result is drastically reduced cache contention and improved use of the limited per-thread cache capacity. For a simulated 16KB L1 cache, MRPB improves the average performance of the entire PolyBench and Rodinia suites by 2.65× and 1.27× respectively, outperforming a state-of-the-art GPU cache management technique.

Original languageEnglish (US)
Title of host publication20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014
PublisherIEEE Computer Society
Pages272-283
Number of pages12
ISBN (Print)9781479930975
DOIs
StatePublished - Jan 1 2014
Event20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014 - Orlando, FL, United States
Duration: Feb 15 2014Feb 19 2014

Publication series

NameProceedings - International Symposium on High-Performance Computer Architecture
ISSN (Print)1530-0897

Other

Other20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014
CountryUnited States
CityOrlando, FL
Period2/15/142/19/14

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

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    Jia, W., Shaw, K. A., & Martonosi, M. R. (2014). MRPB: Memory request prioritization for massively parallel processors. In 20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014 (pp. 272-283). [6835938] (Proceedings - International Symposium on High-Performance Computer Architecture). IEEE Computer Society. https://doi.org/10.1109/HPCA.2014.6835938