MORC: A manycore-oriented compressed cache

Tri M. Nguyen, David Wentzlaff

Research output: Chapter in Book/Report/Conference proceedingConference contribution

19 Scopus citations


Cache compression has largely focused on improving single-stream application performance. In contrast, this work proposes utilizing cache compression to improve application throughput for manycore processors while potentially harming single-stream performance. The growing interest in throughput-oriented manycore architectures and widening disparity between on-chip resources and off-chip bandwidth motivate re-evaluation of utilizing costly compression to conserve off-chip memory bandwidth. This work proposes MORC, a Many-core ORiented Compressed Cache architecture that compresses hundreds of cache lines together to maximize compression ratio. By looking across cache lines, MORC is able to achieve compression ratios beyond compression schemes which only compress within a single cache line. MORC utilizes a novel log-based cache organization which selects cache lines that are filled into the cache close in time as candidates to compress together. The proposed design not only compresses cache data, but also cache tags together to further save storage. Future manycore processors will likely have reduced cache sizes and less bandwidth per core than current multicore processors. We evaluate MORC on such future many-core processors utilizing the SPEC2006 benchmark suite. We find that MORC offers 37% more throughput than uncompressed caches and 17% more throughput than the next best cache compression scheme, while simultaneously reducing 17% of memory system energy compared to uncompressed caches.

Original languageEnglish (US)
Title of host publicationProceedings - 48th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2015
PublisherIEEE Computer Society
Number of pages13
ISBN (Electronic)9781450340342
StatePublished - Dec 5 2015
Event48th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2015 - Waikiki, United States
Duration: Dec 5 2015Dec 9 2015

Publication series

NameProceedings of the Annual International Symposium on Microarchitecture, MICRO
ISSN (Print)1072-4451


Other48th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2015
Country/TerritoryUnited States

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture


  • caches
  • compression
  • manycore


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