Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation

Xinping Zhu, Wei Qin, Sharad Malik

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Scopus citations

Abstract

In multiprocessor based SoCs, optimizing the communication architecture is often as important as, if not more than, optimizing the computation architecture. While there are mature platforms and techniques for the modeling and evaluation of computation architectures, the same is not true for the communication architectures. A major challenge in modeling the communication architecture is managing the concurrency at multiple levels: at the operation level, multiple communication operations may be active at any time; at the microarchitecture level, several microarchitectural components may be operating in parallel. Further, it is important to be able to clearly specify how the operation level concurrency maps to the microarchitectural level concurrency. This paper presents a modeling methodology and a retargetable simulation framework which fill this gap. This framework seeks to facilitate the design space exploration of the communication sub-system through a rigorous modeling approach based on a formal concurrency model, the Operation State Machine (OSM). We first introduce the basic notions and concepts of OSM and show by example how this model can be used to represent the inherent concurrency in the architecture and microarchitecture of processors. Then we demonstrate the applicability of OSM in modeling on-chip communication architectures (OCAs) by walking though a router based packet switching network example and a bus example. Due to the fact that the OSM model is naturally suited to handle the operation and microarchitecture level concurrencies of OCAs as well, our OSM-based modeling methodology enables the entire system including both the computation and communication architectures to be modeled in a single OSM framework. This allows us to develop a tool set that can synthesize cycle-accurate system simulators for multi-PE SoC prototypes. To demonstrate the flexibility of this methodology, we choose two distinct system configurations with different types of OCA: a 4×4 mesh network of 16 PEs, and a cluster of 4 PEs connected by a bus. We show that by simulation, critical system information such as timing and communication patterns can be obtained and evaluated. Consequently, system-level design choices regarding the communication architecture can be made with high confidence in early stages of design. In addition to improving design quality, this methodology also results in significantly shortened design-time.

Original languageEnglish (US)
Title of host publicationInternational Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2004
PublisherAssociation for Computing Machinery (ACM)
Pages66-71
Number of pages6
ISBN (Print)1581139373, 9781581139372
DOIs
StatePublished - 2004
EventSecond IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2004 - Stockholm, Sweden
Duration: Sep 8 2004Sep 10 2004

Publication series

NameSecond IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and Systems Synthesis, CODES+ISSS 2004

Other

OtherSecond IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2004
CountrySweden
CityStockholm
Period9/8/049/10/04

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Keywords

  • Bus
  • Design exploration
  • Multiprocessor system
  • On-chip communication architecture
  • Packet-switching network
  • Retargetable simulation
  • Simulator synthesis

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