MOCSYN: Multiobjective core-based single-chip system synthesis

Robert P. Dick, Niraj Kumar Jha

Research output: Contribution to journalConference article

67 Scopus citations

Abstract

In this paper we present a system synthesis algorithm, called MOCSYN, which partitions and schedules embedded system specifications to intellectual property cores in an integrated circuit. Given a system specification consisting of multiple periodic task graphs as well as a database of core and integrated circuit characteristics, MOCSYN synthesizes real-time heterogeneous single-chip hardware software architectures using an adaptive multiobjective genetic algorithm that is designed to escape local minima. The use of multiobjective optimization allows a single system synthesis run to produce multiple designs which trade off different architectural features. Integrated circuit price, power consumption, and area are optimized under hard real-time constraints. MOCSYN differs from previous work by considering problems unique to single-chip systems. It solves the problem of providing clock signals to cores composing a system-on-a-chip. It produces a bus structure which balances ease of layout with the reduction of bus contention. In addition, it carries out floorplan block placement within its inner loop allowing accurate estimation of global communication delays and power consumption.

Original languageEnglish (US)
Article number761132
Pages (from-to)263-270
Number of pages8
JournalProceedings -Design, Automation and Test in Europe, DATE
DOIs
StatePublished - Dec 1 1999
EventDesign, Automation and Test in Europe Conference and Exhibition 1999, DATE 1999 - Munich, Germany
Duration: Mar 9 1999Mar 12 1999

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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