Micro-architecture issues of predicated execution

Zhenghong Wang, Ruby B. Lee

Research output: Contribution to journalConference articlepeer-review


Predicated execution appears to be a promising way to exploit more Instruction Level Parallelism. By eliminating conditional branches, branch penalties can be reduced and the size of basic blocks can be increased, further facilitating compiler optimizations. Past work on predicated execution focused almost entirely on compiler issues. In this paper, we analyze the impact of predicated execution on the pipeline control of out-of-order and in-order superscalar machines. We show problems arising in implementing predication and propose both conservative and aggressive solutions.

Original languageEnglish (US)
Pages (from-to)349-354
Number of pages6
JournalConference Record of the Asilomar Conference on Signals, Systems and Computers
StatePublished - 2003
EventConference Record of the Thirty-Seventh Asilomar Conference on Signals, Systems and Computers - Pacific Grove, CA, United States
Duration: Nov 9 2003Nov 12 2003

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Computer Networks and Communications


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