Memory performance optimizations for real-time software HDTV decoding

Han Chen, Kai Li, Bin Wei

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

This paper shows that the performance bottleneck in software MPEG-2 video decoders has shifted to memory operations, as microprocessor technologies have been improving at a fast rate during the past few years. We exploit concurrencies between the processor and the memory sub-system at macroblock level to alleviate the performance bottleneck. First, the paper introduces an interleaved-block order data layout to improve cache performance. Second, the paper describes an algorithm to explicitly prefetch macroblocks for motion compensation. Finally, the paper presents an algorithm to schedule interleaved decoding and output at macroblock level. Our implementation and experiments show that these methods successfully hide the latency of memory and frame buffer. These techniques improve the performance of an already optimized software MPEG-2 decoder by about a factor of two. On a 933 MHz Pentium III PC, the decoder can play 720p HDTV streams at over 62 frames per second.

Original languageEnglish (US)
Title of host publicationProceedings - 2002 IEEE International Conference on Multimedia and Expo, ICME 2002
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages305-308
Number of pages4
ISBN (Electronic)0780373049
DOIs
StatePublished - Jan 1 2002
Event2002 IEEE International Conference on Multimedia and Expo, ICME 2002 - Lausanne, Switzerland
Duration: Aug 26 2002Aug 29 2002

Publication series

NameProceedings - 2002 IEEE International Conference on Multimedia and Expo, ICME 2002
Volume1

Other

Other2002 IEEE International Conference on Multimedia and Expo, ICME 2002
CountrySwitzerland
CityLausanne
Period8/26/028/29/02

All Science Journal Classification (ASJC) codes

  • Archaeology
  • Electrical and Electronic Engineering

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