Memory bank and register allocation in software synthesis for ASIPs

Ashok Sudarsanam, Sharad Malik

Research output: Contribution to journalConference articlepeer-review

52 Scopus citations


An architectural feature commonly found in digital signal processors (DSPs) is multiple data-memory banks. This feature increases memory bandwidth by permitting multiple memory accesses to occur in parallel when the referenced variables belong to different memory banks and the registers involved are allocated according to a strict set of conditions. Unfortunately, current compiler technology is unable to take advantage of the potential increase in parallelism offered by such architectures. Consequently, most application software for DSP systems is hand-written - a very time-consuming task. We present an algorithm which attempts to maximize the benefit of this architectural feature. While previous approaches have decoupled the phases of register allocation and memory bank assignment, our algorithm performs these two phases simultaneously. Experimental results demonstrate that our algorithm substantially improves the code quality of many compiler-generated and even hand-written programs.

Original languageEnglish (US)
Pages (from-to)388-392
Number of pages5
JournalIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
StatePublished - 1995
EventProceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design - San Jose, CA, USA
Duration: Nov 5 1995Nov 9 1995

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design


Dive into the research topics of 'Memory bank and register allocation in software synthesis for ASIPs'. Together they form a unique fingerprint.

Cite this