Memory access optimization of motion estimation algorithms on a native SIMD PLX processor

Guang Huei Lin; Sao Jie Chen; Ruby B. Lee; Yu Hen Hu

doi:10.1109/APCCAS.2006.342051

Memory access optimization of motion estimation algorithms on a native SIMD PLX processor

Guang Huei Lin, Sao Jie Chen, Ruby B. Lee, Yu Hen Hu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Scopus citations

Abstract

With mostly non-sequential reference, memory access becomes the bottleneck of SIMD processor performance. In this paper, we present an approach for optimal H.264 motion estimation code generation over a SIMD platform with the objective to minimize memory access overhead. Specifically, we formulate the code generation task as a constrained optimization problem where the objective function is to minimize the amount of memory access overhead, subject to the constraint of the data-dependencies the algorithm. The target platform is based on a native SIMD processor architecture known as PLX developed at Princeton University. We illustrate with an example of generating PLX code for the H.264 variable-block size motion estimation algorithm. We show that the optimization yields significant performance enhancement.

Original language	English (US)
Title of host publication	APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
Pages	566-569
Number of pages	4
DOIs	https://doi.org/10.1109/APCCAS.2006.342051
State	Published - 2006
Event	APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems - , Singapore Duration: Dec 4 2006 → Dec 6 2006

Publication series

Name	IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Other

Other	APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
Country/Territory	Singapore
Period	12/4/06 → 12/6/06

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Keywords

Memory access
SIMD
Software pipelining

Access to Document

10.1109/APCCAS.2006.342051

Cite this

Lin, G. H., Chen, S. J., Lee, R. B., & Hu, Y. H. (2006). Memory access optimization of motion estimation algorithms on a native SIMD PLX processor. In APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems (pp. 566-569). Article 4145456 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS). https://doi.org/10.1109/APCCAS.2006.342051

@inproceedings{02b00d10ad0e4e608068774c997edf26,

title = "Memory access optimization of motion estimation algorithms on a native SIMD PLX processor",

abstract = "With mostly non-sequential reference, memory access becomes the bottleneck of SIMD processor performance. In this paper, we present an approach for optimal H.264 motion estimation code generation over a SIMD platform with the objective to minimize memory access overhead. Specifically, we formulate the code generation task as a constrained optimization problem where the objective function is to minimize the amount of memory access overhead, subject to the constraint of the data-dependencies the algorithm. The target platform is based on a native SIMD processor architecture known as PLX developed at Princeton University. We illustrate with an example of generating PLX code for the H.264 variable-block size motion estimation algorithm. We show that the optimization yields significant performance enhancement.",

keywords = "Memory access, SIMD, Software pipelining",

author = "Lin, {Guang Huei} and Chen, {Sao Jie} and Lee, {Ruby B.} and Hu, {Yu Hen}",

year = "2006",

doi = "10.1109/APCCAS.2006.342051",

language = "English (US)",

isbn = "1424403871",

series = "IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS",

pages = "566--569",

booktitle = "APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems",

note = "APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems ; Conference date: 04-12-2006 Through 06-12-2006",

}

Lin, GH, Chen, SJ, Lee, RB & Hu, YH 2006, Memory access optimization of motion estimation algorithms on a native SIMD PLX processor. in APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems., 4145456, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, pp. 566-569, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems, Singapore, 12/4/06. https://doi.org/10.1109/APCCAS.2006.342051

Memory access optimization of motion estimation algorithms on a native SIMD PLX processor. / Lin, Guang Huei; Chen, Sao Jie; Lee, Ruby B. et al.
APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems. 2006. p. 566-569 4145456 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Memory access optimization of motion estimation algorithms on a native SIMD PLX processor

AU - Lin, Guang Huei

AU - Chen, Sao Jie

AU - Lee, Ruby B.

AU - Hu, Yu Hen

PY - 2006

Y1 - 2006

N2 - With mostly non-sequential reference, memory access becomes the bottleneck of SIMD processor performance. In this paper, we present an approach for optimal H.264 motion estimation code generation over a SIMD platform with the objective to minimize memory access overhead. Specifically, we formulate the code generation task as a constrained optimization problem where the objective function is to minimize the amount of memory access overhead, subject to the constraint of the data-dependencies the algorithm. The target platform is based on a native SIMD processor architecture known as PLX developed at Princeton University. We illustrate with an example of generating PLX code for the H.264 variable-block size motion estimation algorithm. We show that the optimization yields significant performance enhancement.

AB - With mostly non-sequential reference, memory access becomes the bottleneck of SIMD processor performance. In this paper, we present an approach for optimal H.264 motion estimation code generation over a SIMD platform with the objective to minimize memory access overhead. Specifically, we formulate the code generation task as a constrained optimization problem where the objective function is to minimize the amount of memory access overhead, subject to the constraint of the data-dependencies the algorithm. The target platform is based on a native SIMD processor architecture known as PLX developed at Princeton University. We illustrate with an example of generating PLX code for the H.264 variable-block size motion estimation algorithm. We show that the optimization yields significant performance enhancement.

KW - Memory access

KW - SIMD

KW - Software pipelining

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M3 - Conference contribution

AN - SCOPUS:50249125395

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T3 - IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

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BT - APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems

T2 - APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems

Y2 - 4 December 2006 through 6 December 2006

ER -

Memory access optimization of motion estimation algorithms on a native SIMD PLX processor

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