MemFlow: Memory-driven data scheduling with datapath co-design in accelerators for large-scale inference applications

Qi Nie; Sharad Malik

doi:10.1109/ASPDAC.2018.8297364

MemFlow: Memory-driven data scheduling with datapath co-design in accelerators for large-scale inference applications

Qi Nie, Sharad Malik

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Scopus citations

Abstract

SRAM scratch-pad memory in accelerators is limited in size and bandwidth. Besides computation, accelerator design is about how data flow is scheduled across the memory hierarchy, from DRAM to datapath registers. There is limited support for this in current tools. Thus, we propose MemFlow, memory-driven data scheduling with datapath co-design in accelerators, to improve computing performance and reduce higher-level memory accesses. We demonstrate its efficacy using several key kernels from large-scale inference applications.

Original language	English (US)
Title of host publication	ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	446-451
Number of pages	6
ISBN (Electronic)	9781509006021
DOIs	https://doi.org/10.1109/ASPDAC.2018.8297364
State	Published - Feb 20 2018
Event	23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018 - Jeju, Korea, Republic of Duration: Jan 22 2018 → Jan 25 2018

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume	2018-January

Other

Other	23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018
Country/Territory	Korea, Republic of
City	Jeju
Period	1/22/18 → 1/25/18

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering
Computer Science Applications
Computer Graphics and Computer-Aided Design

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10.1109/ASPDAC.2018.8297364

Cite this

Nie, Q., & Malik, S. (2018). MemFlow: Memory-driven data scheduling with datapath co-design in accelerators for large-scale inference applications. In ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings (pp. 446-451). (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 2018-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2018.8297364

Nie, Qi ; Malik, Sharad. / MemFlow : Memory-driven data scheduling with datapath co-design in accelerators for large-scale inference applications. ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 446-451 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

@inproceedings{b2438613e9a942d8be7314bd572d3fec,

title = "MemFlow: Memory-driven data scheduling with datapath co-design in accelerators for large-scale inference applications",

abstract = "SRAM scratch-pad memory in accelerators is limited in size and bandwidth. Besides computation, accelerator design is about how data flow is scheduled across the memory hierarchy, from DRAM to datapath registers. There is limited support for this in current tools. Thus, we propose MemFlow, memory-driven data scheduling with datapath co-design in accelerators, to improve computing performance and reduce higher-level memory accesses. We demonstrate its efficacy using several key kernels from large-scale inference applications.",

author = "Qi Nie and Sharad Malik",

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Nie, Q & Malik, S 2018, MemFlow: Memory-driven data scheduling with datapath co-design in accelerators for large-scale inference applications. in ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, vol. 2018-January, Institute of Electrical and Electronics Engineers Inc., pp. 446-451, 23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018, Jeju, Korea, Republic of, 1/22/18. https://doi.org/10.1109/ASPDAC.2018.8297364

MemFlow: Memory-driven data scheduling with datapath co-design in accelerators for large-scale inference applications. / Nie, Qi; Malik, Sharad.
ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. p. 446-451 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 2018-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N2 - SRAM scratch-pad memory in accelerators is limited in size and bandwidth. Besides computation, accelerator design is about how data flow is scheduled across the memory hierarchy, from DRAM to datapath registers. There is limited support for this in current tools. Thus, we propose MemFlow, memory-driven data scheduling with datapath co-design in accelerators, to improve computing performance and reduce higher-level memory accesses. We demonstrate its efficacy using several key kernels from large-scale inference applications.

AB - SRAM scratch-pad memory in accelerators is limited in size and bandwidth. Besides computation, accelerator design is about how data flow is scheduled across the memory hierarchy, from DRAM to datapath registers. There is limited support for this in current tools. Thus, we propose MemFlow, memory-driven data scheduling with datapath co-design in accelerators, to improve computing performance and reduce higher-level memory accesses. We demonstrate its efficacy using several key kernels from large-scale inference applications.

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Nie Q, Malik S. MemFlow: Memory-driven data scheduling with datapath co-design in accelerators for large-scale inference applications. In ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings. Institute of Electrical and Electronics Engineers Inc. 2018. p. 446-451. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). doi: 10.1109/ASPDAC.2018.8297364

MemFlow: Memory-driven data scheduling with datapath co-design in accelerators for large-scale inference applications

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