TY - JOUR
T1 - Mcpat-monolithic
T2 - An area/power/timing architecture modeling framework for 3-d hybrid monolithic multicore systems
AU - Guler, Abdullah
AU - Jha, Niraj K.
N1 - Funding Information:
Manuscript received January 12, 2020; revised May 2, 2020 and May 25, 2020; accepted June 9, 2020. Date of publication June 25, 2020; date of current version September 25, 2020. This work was supported by the National Science Foundation under Grant CCF-1714161 and Grant CCF-1811109. (Corresponding author: Abdullah Guler.) The authors are with the Department of Electrical Engineering, Princeton University, Princeton, NJ 08544 USA (e-mail: aguler@princeton.edu; jha@princeton.edu).
Publisher Copyright:
© 1993-2012 IEEE.
PY - 2020/10
Y1 - 2020/10
N2 - Three-dimensional integrated circuits (3-D ICs) have the potential to push Moore's law further by accommodating more transistors per unit footprint area along with a reduction in power consumption, interconnect length, and the number of repeaters. Monolithic 3-D integration is particularly promising in this regard as it offers a very high connectivity between vertical transistor layers owing to its nanoscale monolithic intertier vias. Monolithic integration can be realized at block-, gate-, and transistor-level granularity. A hybrid monolithic (HM) design aims to further optimize area, power, and performance of the chip by combining different monolithic styles. In this article, we introduce McPAT-monolithic, a framework for modeling HM multicore architectures. We use the OpenSPARC T2 processor as a case study to compare different monolithic implementation styles and explore the benefits of HM design. Our simulations show that, under the same timing constraint, an HM design offers 47.2% reduction in footprint area and 5.3% in power consumption compared to a 2-D design at the cost of slightly higher on-chip temperature.
AB - Three-dimensional integrated circuits (3-D ICs) have the potential to push Moore's law further by accommodating more transistors per unit footprint area along with a reduction in power consumption, interconnect length, and the number of repeaters. Monolithic 3-D integration is particularly promising in this regard as it offers a very high connectivity between vertical transistor layers owing to its nanoscale monolithic intertier vias. Monolithic integration can be realized at block-, gate-, and transistor-level granularity. A hybrid monolithic (HM) design aims to further optimize area, power, and performance of the chip by combining different monolithic styles. In this article, we introduce McPAT-monolithic, a framework for modeling HM multicore architectures. We use the OpenSPARC T2 processor as a case study to compare different monolithic implementation styles and explore the benefits of HM design. Our simulations show that, under the same timing constraint, an HM design offers 47.2% reduction in footprint area and 5.3% in power consumption compared to a 2-D design at the cost of slightly higher on-chip temperature.
KW - Area/timing/power models
KW - McPAT
KW - hybrid floorplanning
KW - monolithic three-dimensional integrated circuits (3-D ICs)
KW - multicore designs
UR - http://www.scopus.com/inward/record.url?scp=85092355426&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85092355426&partnerID=8YFLogxK
U2 - 10.1109/TVLSI.2020.3002723
DO - 10.1109/TVLSI.2020.3002723
M3 - Article
AN - SCOPUS:85092355426
SN - 1063-8210
VL - 28
SP - 2146
EP - 2156
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 10
M1 - 9126203
ER -