Maximum frequency of operation of CMOS static frequency dividers: Theory and design techniques

Kaushik Sengupta, Hossein Hashemi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Scopus citations

Abstract

This paper presents a theoretical analysis of the maximum frequency of operation of CMOS static frequency dividers. The approach is based on the transient analysis of output voltages derived from differential equations of the large-signal model of the circuit. Tradeoffs and design techniques for very high frequency dividers have been discussed on the basis of the derived expression. An inductor-less 45 GHz divider and a shunt-peaked 60 GHz divider have been designed in 0.13 μm process following the suggested design techniques. Detailed simulaton results have been presented.

Original languageEnglish (US)
Title of host publicationICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems
Pages584-587
Number of pages4
DOIs
StatePublished - Dec 1 2006
Externally publishedYes
EventICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems - Nice, France
Duration: Dec 10 2006Dec 13 2006

Publication series

NameProceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Other

OtherICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems
CountryFrance
CityNice
Period12/10/0612/13/06

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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    Sengupta, K., & Hashemi, H. (2006). Maximum frequency of operation of CMOS static frequency dividers: Theory and design techniques. In ICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems (pp. 584-587). [4263434] (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems). https://doi.org/10.1109/ICECS.2006.379856