MAPPING DIGITAL SIGNAL PROCESSING ALGORITHMS ONTO VLSI SYSTOLIC/WAVEFRONT ARRAYS.

S. Y. Kung, J. N. Hwang, S. C. Lo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

The authors propose a coherent methodology for the systematic mapping from digital signal processing algorithms to algorithm-specialized systolic arrays. The mapping process is divided into three stages: (1) deriving a local (data) dependent graph (DG) from the given algorithm; (2) projecting the DG onto lower-dimensional signal flow graphs (SFGs); and (3) transforming the SFG into a systolic array by cut-set systolization or into a wavefront array by a formal procedure. This design methodology is demonstrated by designing systolic arrays for several important algorithms.

Original languageEnglish (US)
Title of host publicationConference Record - Asilomar Conference on Circuits, Systems & Computers
PublisherIEEE
Pages6-12
Number of pages7
ISBN (Print)0818608161
StatePublished - Jan 1 1987
Externally publishedYes

Publication series

NameConference Record - Asilomar Conference on Circuits, Systems & Computers
ISSN (Print)0736-5861

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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  • Cite this

    Kung, S. Y., Hwang, J. N., & Lo, S. C. (1987). MAPPING DIGITAL SIGNAL PROCESSING ALGORITHMS ONTO VLSI SYSTOLIC/WAVEFRONT ARRAYS. In Conference Record - Asilomar Conference on Circuits, Systems & Computers (pp. 6-12). (Conference Record - Asilomar Conference on Circuits, Systems & Computers). IEEE.