MAPPING DIGITAL SIGNAL PROCESSING ALGORITHMS ONTO VLSI SYSTOLIC/WAVEFRONT ARRAYS.

S. Y. Kung; J. N. Hwang; S. C. Lo

MAPPING DIGITAL SIGNAL PROCESSING ALGORITHMS ONTO VLSI SYSTOLIC/WAVEFRONT ARRAYS.

S. Y. Kung, J. N. Hwang, S. C. Lo

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

The authors propose a coherent methodology for the systematic mapping from digital signal processing algorithms to algorithm-specialized systolic arrays. The mapping process is divided into three stages: (1) deriving a local (data) dependent graph (DG) from the given algorithm; (2) projecting the DG onto lower-dimensional signal flow graphs (SFGs); and (3) transforming the SFG into a systolic array by cut-set systolization or into a wavefront array by a formal procedure. This design methodology is demonstrated by designing systolic arrays for several important algorithms.

Original language	English (US)
Title of host publication	Conference Record - Asilomar Conference on Circuits, Systems & Computers
Publisher	IEEE
Pages	6-12
Number of pages	7
ISBN (Print)	0818608161
State	Published - 1987
Externally published	Yes

Publication series

Name	Conference Record - Asilomar Conference on Circuits, Systems & Computers
ISSN (Print)	0736-5861

All Science Journal Classification (ASJC) codes

General Engineering

Cite this

@inproceedings{834c6f1cdc674707b5df9cc039f44b26,

title = "MAPPING DIGITAL SIGNAL PROCESSING ALGORITHMS ONTO VLSI SYSTOLIC/WAVEFRONT ARRAYS.",

abstract = "The authors propose a coherent methodology for the systematic mapping from digital signal processing algorithms to algorithm-specialized systolic arrays. The mapping process is divided into three stages: (1) deriving a local (data) dependent graph (DG) from the given algorithm; (2) projecting the DG onto lower-dimensional signal flow graphs (SFGs); and (3) transforming the SFG into a systolic array by cut-set systolization or into a wavefront array by a formal procedure. This design methodology is demonstrated by designing systolic arrays for several important algorithms.",

author = "Kung, {S. Y.} and Hwang, {J. N.} and Lo, {S. C.}",

year = "1987",

language = "English (US)",

isbn = "0818608161",

series = "Conference Record - Asilomar Conference on Circuits, Systems & Computers",

publisher = "IEEE",

pages = "6--12",

booktitle = "Conference Record - Asilomar Conference on Circuits, Systems & Computers",

}

MAPPING DIGITAL SIGNAL PROCESSING ALGORITHMS ONTO VLSI SYSTOLIC/WAVEFRONT ARRAYS. / Kung, S. Y.; Hwang, J. N.; Lo, S. C.
Conference Record - Asilomar Conference on Circuits, Systems & Computers. IEEE, 1987. p. 6-12 (Conference Record - Asilomar Conference on Circuits, Systems & Computers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - MAPPING DIGITAL SIGNAL PROCESSING ALGORITHMS ONTO VLSI SYSTOLIC/WAVEFRONT ARRAYS.

AU - Kung, S. Y.

AU - Hwang, J. N.

AU - Lo, S. C.

PY - 1987

Y1 - 1987

N2 - The authors propose a coherent methodology for the systematic mapping from digital signal processing algorithms to algorithm-specialized systolic arrays. The mapping process is divided into three stages: (1) deriving a local (data) dependent graph (DG) from the given algorithm; (2) projecting the DG onto lower-dimensional signal flow graphs (SFGs); and (3) transforming the SFG into a systolic array by cut-set systolization or into a wavefront array by a formal procedure. This design methodology is demonstrated by designing systolic arrays for several important algorithms.

AB - The authors propose a coherent methodology for the systematic mapping from digital signal processing algorithms to algorithm-specialized systolic arrays. The mapping process is divided into three stages: (1) deriving a local (data) dependent graph (DG) from the given algorithm; (2) projecting the DG onto lower-dimensional signal flow graphs (SFGs); and (3) transforming the SFG into a systolic array by cut-set systolization or into a wavefront array by a formal procedure. This design methodology is demonstrated by designing systolic arrays for several important algorithms.

UR - http://www.scopus.com/inward/record.url?scp=0023173150&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0023173150&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0023173150

SN - 0818608161

T3 - Conference Record - Asilomar Conference on Circuits, Systems & Computers

SP - 6

EP - 12

BT - Conference Record - Asilomar Conference on Circuits, Systems & Computers

PB - IEEE

ER -

MAPPING DIGITAL SIGNAL PROCESSING ALGORITHMS ONTO VLSI SYSTOLIC/WAVEFRONT ARRAYS.

Abstract

Publication series

All Science Journal Classification (ASJC) codes

Other files and links

Fingerprint

Cite this