Managing leakage for transient data: Decay and quasi-static 4T memory cells

Zhigang Hu, Philo Juang, Phil Diodato, Stefanos Kaxiras, Kevin Skadron, Margaret Rose Martonosi, Douglas W. Clark

Research output: Contribution to conferencePaper

21 Scopus citations

Abstract

Much of on-chip storage is devoted to transient, often short-lived, data. Despite this, virtually all on-chip array structures use six-transistor (6T) static RAM cells that store data indefinitely. In this paper we propose the use of quasi-static four-transistor (4T) RAM cells. Quasi-static 4T cells provide both energy and area savings. These cells have no connection to Vdd and thus inherently provide decay functionality: values are refreshed upon access but discharge over time without use. This makes 4T cells uniquely well-suited for predictive structures like branch predictors and BTBs where data integrity is not essential. We use quantitative evaluations (both circuit-level and cycle-level) to explore the design space and quantify the opportunities. Overall, 4T-based branch predictors offer 12-33% area savings and 60-80% leakage savings with minimal performance impact. More broadly, this paper suggests a new view of how to support transient data in power-aware processors.

Original languageEnglish (US)
Pages52-55
Number of pages4
StatePublished - Dec 1 2002
EventProceedings of the 2002 International Symposium on Low Power Electronics and Design - Monterey, CA, United States
Duration: Aug 12 2002Aug 14 2002

Other

OtherProceedings of the 2002 International Symposium on Low Power Electronics and Design
CountryUnited States
CityMonterey, CA
Period8/12/028/14/02

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Fingerprint Dive into the research topics of 'Managing leakage for transient data: Decay and quasi-static 4T memory cells'. Together they form a unique fingerprint.

  • Cite this

    Hu, Z., Juang, P., Diodato, P., Kaxiras, S., Skadron, K., Martonosi, M. R., & Clark, D. W. (2002). Managing leakage for transient data: Decay and quasi-static 4T memory cells. 52-55. Paper presented at Proceedings of the 2002 International Symposium on Low Power Electronics and Design, Monterey, CA, United States.