This research examines the role of dynamically reconfigurable logic in systems-on-a-chip (SoC) design. Specifically we study the overhead of storing and downloading the configuration code bits for different parts of an application in a dynamically reconfigurable coprocessor environment. For SoC designs the different configuration bit-streams will likely need to be stored on chip, thus it becomes crucial to reduce the storage overhead. In addition, reducing the reconfiguration time overhead is crucial in realizing performance benefits. This study provides insight into the granularity of the reconfigurable logic that is appropriate for the SoC context. Our initial study is in the domain of multimedia and communication systems. We first present profiling results for these using the MESCAL compiler infrastructure. These results are used to derive an architecture template that consists of dynamically reconfigurable datapaths using coarse grain logic blocks and a reconfigurable interconnection network. We justify this template based on the constraints of SoC design. We then describe a design flow where we start from an application, derive the kernel loops via profiling and then map the application using the dynamically reconfigurable datapath and the simplest interconnection network. As part of this flow we have developed a mapping algorithm that minimizes the size of the interconnection network and thus the overhead of reconfiguration, which is key for systems-on-a-chip. We provide some initial results that validate our approach.
|Original language||English (US)|
|Number of pages||6|
|Journal||Proceedings -Design, Automation and Test in Europe, DATE|
|State||Published - Dec 1 2001|
|Event||Design, Automation and Test in Europe Conference and Exhibition 2001, DATE 2001 - Munich, Germany|
Duration: Mar 13 2001 → Mar 16 2001
All Science Journal Classification (ASJC) codes