TY - JOUR
T1 - Majority and minority network synthesis with application to QCA-, SET-, and TPL-based nanotechnologies
AU - Zhang, Rui
AU - Gupta, Pallav
AU - Jha, Niraj K.
N1 - Funding Information:
Manuscript received July 22, 2005; revised August 11, 2006. This work was supported by the NSF under Grant CCR-0303789. This paper was recommended by Associate Editor M. Poncino. R. Zhang is with the Mentor Graphics Corporation, San Jose, CA 95131 USA. P. Gupta and N. K. Jha are with the Department of Electrical Engineering, Princeton University, Princeton, NJ 08544 USA (e-mail: pgupta@princeton. edu; [email protected]). Digital Object Identifier 10.1109/TCAD.2006.888267
PY - 2007/7
Y1 - 2007/7
N2 - In this paper, we present a methodology for efficient majority/minority network synthesis of arbitrary multiout-put Boolean functions. Many emerging nanoscale technologies, such as quantum cellular automata (QCA), single electron tunneling (SET), and tunneling phase logic (TPL), are capable of implementing majority or minority logic very efficiently. The main purpose of this paper is to lay the foundation for research on the development of synthesis methodologies and tools to generate optimized majority/minority networks for these emergent technologies. Functionally correct QCA-, SET-, and TPL-based majority/minority gates have been successfully demonstrated. However, there exists no comprehensive methodology or design automation tool for general multilevel majority/minority network synthesis. We have built the first such tool, MAjority Logic Synthesizer, on top of an existing Boolean logic synthesis tool. Experiments with 40 Microelectronics Center of North Carolina benchmarks were performed. They indicate that up to 68.0% reduction in gate count is possible when utilizing majority/minority logic, with the average reduction being 21.9%, compared to traditional logic synthesis, in which two-input AND/OR gates in the circuit are converted to majority/minority gates.
AB - In this paper, we present a methodology for efficient majority/minority network synthesis of arbitrary multiout-put Boolean functions. Many emerging nanoscale technologies, such as quantum cellular automata (QCA), single electron tunneling (SET), and tunneling phase logic (TPL), are capable of implementing majority or minority logic very efficiently. The main purpose of this paper is to lay the foundation for research on the development of synthesis methodologies and tools to generate optimized majority/minority networks for these emergent technologies. Functionally correct QCA-, SET-, and TPL-based majority/minority gates have been successfully demonstrated. However, there exists no comprehensive methodology or design automation tool for general multilevel majority/minority network synthesis. We have built the first such tool, MAjority Logic Synthesizer, on top of an existing Boolean logic synthesis tool. Experiments with 40 Microelectronics Center of North Carolina benchmarks were performed. They indicate that up to 68.0% reduction in gate count is possible when utilizing majority/minority logic, with the average reduction being 21.9%, compared to traditional logic synthesis, in which two-input AND/OR gates in the circuit are converted to majority/minority gates.
KW - Design automation
KW - Logic synthesis
KW - Majority networks
KW - Quantum cellular automata (QCA)
KW - Single electron tunneling (SET)
UR - http://www.scopus.com/inward/record.url?scp=34250745244&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=34250745244&partnerID=8YFLogxK
U2 - 10.1109/TCAD.2006.888267
DO - 10.1109/TCAD.2006.888267
M3 - Article
AN - SCOPUS:34250745244
SN - 0278-0070
VL - 26
SP - 1233
EP - 1245
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IS - 7
M1 - 4237247
ER -