TY - GEN
T1 - LUCIE
T2 - 57th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2024
AU - Li, Zixi
AU - Wentzlaff, David
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - Multi-chip modules, recently also known as chiplets, are a promising approach to building large-scale silicon in the post-Moore's Law era. While chiplet-based designs offer advantages like averting manufacturing yield issues and enabling heterogeneous integration, there has not been a standard for seamless communication and integration of chiplets. This paper proposes LUCIE, a Lightweight Universal Chiplet-Interposer Ecosystem that provides a universal, modular, and reconfigurable framework for plug-And-play integration of chiplets. The key ideas behind LUCIE include a flexible 2D grid-based interposer design and a placement tool to aid chiplet integration. Its lightweight design and direct connection between chiplets allowed designs to fit into the LUCIE framework with minimal effort while achieving great performance. Performance analysis showed that LUCIE's performance is comparable to custom interposers, up to twice as fast as NoC-on-NoP designs in certain scenarios, and around 20% more power efficient than NoC-on-NoP designs. Compared to using custom interposers, cost analysis showed that LUCIE saves up to 18.9% of manufacturing cost, 60,000 of Non-Recurring Engineering cost, and 30 weeks less time-To-market. The LUCIE framework is more flexible and ideal for more topologies, such as 2D mesh and star topology. With the development of a novel, graph-based placement algorithm, LUCIE significantly reduces design complexity compared to monolithic and custom interposer-based chiplet systems while providing a high degree of modularity and reconfigurability.
AB - Multi-chip modules, recently also known as chiplets, are a promising approach to building large-scale silicon in the post-Moore's Law era. While chiplet-based designs offer advantages like averting manufacturing yield issues and enabling heterogeneous integration, there has not been a standard for seamless communication and integration of chiplets. This paper proposes LUCIE, a Lightweight Universal Chiplet-Interposer Ecosystem that provides a universal, modular, and reconfigurable framework for plug-And-play integration of chiplets. The key ideas behind LUCIE include a flexible 2D grid-based interposer design and a placement tool to aid chiplet integration. Its lightweight design and direct connection between chiplets allowed designs to fit into the LUCIE framework with minimal effort while achieving great performance. Performance analysis showed that LUCIE's performance is comparable to custom interposers, up to twice as fast as NoC-on-NoP designs in certain scenarios, and around 20% more power efficient than NoC-on-NoP designs. Compared to using custom interposers, cost analysis showed that LUCIE saves up to 18.9% of manufacturing cost, 60,000 of Non-Recurring Engineering cost, and 30 weeks less time-To-market. The LUCIE framework is more flexible and ideal for more topologies, such as 2D mesh and star topology. With the development of a novel, graph-based placement algorithm, LUCIE significantly reduces design complexity compared to monolithic and custom interposer-based chiplet systems while providing a high degree of modularity and reconfigurability.
KW - Chiplets
KW - Cost analysis
KW - Heterogeneous integration
KW - Multichip modules
UR - http://www.scopus.com/inward/record.url?scp=85213299353&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85213299353&partnerID=8YFLogxK
U2 - 10.1109/MICRO61859.2024.00039
DO - 10.1109/MICRO61859.2024.00039
M3 - Conference contribution
AN - SCOPUS:85213299353
T3 - Proceedings of the Annual International Symposium on Microarchitecture, MICRO
SP - 423
EP - 436
BT - Proceedings - 2024 57th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2024
PB - IEEE Computer Society
Y2 - 2 November 2024 through 6 November 2024
ER -