Low-power FinFET design schemes for NOR address decoders

Michael A. Turi; José G. Delgado-Frias; Niraj K. Jha

doi:10.1109/VDAT.2010.5496695

Low-power FinFET design schemes for NOR address decoders

Michael A. Turi, José G. Delgado-Frias, Niraj K. Jha

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

7 Scopus citations

Abstract

This paper presents and evaluates six novel, low-power, FinFET-based design schemes of the conventional NOR address decoder. These schemes differ in front- and back-gate connections and input signal swing. Simulations of these schemes were performed using a 32nm FinFET technology model and the schemes' performance was evaluated in terms of dynamic current consumption, delay, and leakage current consumption. The Low-Power (LP) scheme, a scheme where the FinFETs' back gates are reverse-biased for lower-power operation, was used as the base scheme for comparisons. The Shorted-Gate (SG) High Precharge Swing scheme has a better performance tradeoff than the other presented schemes, including the LP scheme. While dynamic power is 10.9% to 11.9% more than the LP scheme, the SG-High Precharge Swing scheme is 48.1% to 59.9% faster and dissipates 93.0% to 99.7% less leakage power than the LP scheme. In addition, the SG-High Precharge Swing scheme requires less supporting hardware as it needs one less voltage level and one less voltage conversion buffer than the LP scheme.

Original language	English (US)
Title of host publication	Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010
Pages	74-77
Number of pages	4
DOIs	https://doi.org/10.1109/VDAT.2010.5496695
State	Published - 2010
Event	2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010 - Hsin Chu, Taiwan, Province of China Duration: Apr 26 2010 → Apr 29 2010

Publication series

Name	Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010

Other

Other	2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010
Country/Territory	Taiwan, Province of China
City	Hsin Chu
Period	4/26/10 → 4/29/10

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Keywords

Address decoders
FinFET circuits
High performance
Low power

Access to Document

10.1109/VDAT.2010.5496695

Cite this

Turi, M. A., Delgado-Frias, J. G., & Jha, N. K. (2010). Low-power FinFET design schemes for NOR address decoders. In Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010 (pp. 74-77). Article 5496695 (Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010). https://doi.org/10.1109/VDAT.2010.5496695

@inproceedings{1b93c0514e59400593a8893580808c9b,

title = "Low-power FinFET design schemes for NOR address decoders",

abstract = "This paper presents and evaluates six novel, low-power, FinFET-based design schemes of the conventional NOR address decoder. These schemes differ in front- and back-gate connections and input signal swing. Simulations of these schemes were performed using a 32nm FinFET technology model and the schemes' performance was evaluated in terms of dynamic current consumption, delay, and leakage current consumption. The Low-Power (LP) scheme, a scheme where the FinFETs' back gates are reverse-biased for lower-power operation, was used as the base scheme for comparisons. The Shorted-Gate (SG) High Precharge Swing scheme has a better performance tradeoff than the other presented schemes, including the LP scheme. While dynamic power is 10.9% to 11.9% more than the LP scheme, the SG-High Precharge Swing scheme is 48.1% to 59.9% faster and dissipates 93.0% to 99.7% less leakage power than the LP scheme. In addition, the SG-High Precharge Swing scheme requires less supporting hardware as it needs one less voltage level and one less voltage conversion buffer than the LP scheme.",

keywords = "Address decoders, FinFET circuits, High performance, Low power",

author = "Turi, {Michael A.} and Delgado-Frias, {Jos{\'e} G.} and Jha, {Niraj K.}",

year = "2010",

doi = "10.1109/VDAT.2010.5496695",

language = "English (US)",

isbn = "9781424452712",

series = "Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010",

pages = "74--77",

booktitle = "Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010",

note = "2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010 ; Conference date: 26-04-2010 Through 29-04-2010",

}

Turi, MA, Delgado-Frias, JG & Jha, NK 2010, Low-power FinFET design schemes for NOR address decoders. in Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010., 5496695, Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010, pp. 74-77, 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010, Hsin Chu, Taiwan, Province of China, 4/26/10. https://doi.org/10.1109/VDAT.2010.5496695

Low-power FinFET design schemes for NOR address decoders. / Turi, Michael A.; Delgado-Frias, José G.; Jha, Niraj K.
Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010. 2010. p. 74-77 5496695 (Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Low-power FinFET design schemes for NOR address decoders

AU - Turi, Michael A.

AU - Delgado-Frias, José G.

AU - Jha, Niraj K.

PY - 2010

Y1 - 2010

N2 - This paper presents and evaluates six novel, low-power, FinFET-based design schemes of the conventional NOR address decoder. These schemes differ in front- and back-gate connections and input signal swing. Simulations of these schemes were performed using a 32nm FinFET technology model and the schemes' performance was evaluated in terms of dynamic current consumption, delay, and leakage current consumption. The Low-Power (LP) scheme, a scheme where the FinFETs' back gates are reverse-biased for lower-power operation, was used as the base scheme for comparisons. The Shorted-Gate (SG) High Precharge Swing scheme has a better performance tradeoff than the other presented schemes, including the LP scheme. While dynamic power is 10.9% to 11.9% more than the LP scheme, the SG-High Precharge Swing scheme is 48.1% to 59.9% faster and dissipates 93.0% to 99.7% less leakage power than the LP scheme. In addition, the SG-High Precharge Swing scheme requires less supporting hardware as it needs one less voltage level and one less voltage conversion buffer than the LP scheme.

AB - This paper presents and evaluates six novel, low-power, FinFET-based design schemes of the conventional NOR address decoder. These schemes differ in front- and back-gate connections and input signal swing. Simulations of these schemes were performed using a 32nm FinFET technology model and the schemes' performance was evaluated in terms of dynamic current consumption, delay, and leakage current consumption. The Low-Power (LP) scheme, a scheme where the FinFETs' back gates are reverse-biased for lower-power operation, was used as the base scheme for comparisons. The Shorted-Gate (SG) High Precharge Swing scheme has a better performance tradeoff than the other presented schemes, including the LP scheme. While dynamic power is 10.9% to 11.9% more than the LP scheme, the SG-High Precharge Swing scheme is 48.1% to 59.9% faster and dissipates 93.0% to 99.7% less leakage power than the LP scheme. In addition, the SG-High Precharge Swing scheme requires less supporting hardware as it needs one less voltage level and one less voltage conversion buffer than the LP scheme.

KW - Address decoders

KW - FinFET circuits

KW - High performance

KW - Low power

UR - http://www.scopus.com/inward/record.url?scp=78049380299&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=78049380299&partnerID=8YFLogxK

U2 - 10.1109/VDAT.2010.5496695

DO - 10.1109/VDAT.2010.5496695

M3 - Conference contribution

AN - SCOPUS:78049380299

SN - 9781424452712

T3 - Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010

SP - 74

EP - 77

BT - Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010

T2 - 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010

Y2 - 26 April 2010 through 29 April 2010

ER -

Low-power FinFET design schemes for NOR address decoders

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Keywords

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