Low-power FinFET design schemes for NOR address decoders

Michael A. Turi, José G. Delgado-Frias, Niraj K. Jha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Scopus citations

Abstract

This paper presents and evaluates six novel, low-power, FinFET-based design schemes of the conventional NOR address decoder. These schemes differ in front- and back-gate connections and input signal swing. Simulations of these schemes were performed using a 32nm FinFET technology model and the schemes' performance was evaluated in terms of dynamic current consumption, delay, and leakage current consumption. The Low-Power (LP) scheme, a scheme where the FinFETs' back gates are reverse-biased for lower-power operation, was used as the base scheme for comparisons. The Shorted-Gate (SG) High Precharge Swing scheme has a better performance tradeoff than the other presented schemes, including the LP scheme. While dynamic power is 10.9% to 11.9% more than the LP scheme, the SG-High Precharge Swing scheme is 48.1% to 59.9% faster and dissipates 93.0% to 99.7% less leakage power than the LP scheme. In addition, the SG-High Precharge Swing scheme requires less supporting hardware as it needs one less voltage level and one less voltage conversion buffer than the LP scheme.

Original languageEnglish (US)
Title of host publicationProceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010
Pages74-77
Number of pages4
DOIs
StatePublished - Nov 8 2010
Event2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010 - Hsin Chu, Taiwan, Province of China
Duration: Apr 26 2010Apr 29 2010

Publication series

NameProceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010

Other

Other2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010
CountryTaiwan, Province of China
CityHsin Chu
Period4/26/104/29/10

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Keywords

  • Address decoders
  • FinFET circuits
  • High performance
  • Low power

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  • Cite this

    Turi, M. A., Delgado-Frias, J. G., & Jha, N. K. (2010). Low-power FinFET design schemes for NOR address decoders. In Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010 (pp. 74-77). [5496695] (Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010). https://doi.org/10.1109/VDAT.2010.5496695