Low-power FinFET circuit synthesis using surface orientation optimization

Engineering

• Logic Gate 100%
• Experimental Result 50%
• Logic Design 50%
• Power Estimate 50%
• Delay Constraint 50%
• Design Style 50%
• Linear Programming 50%
• Area Estimate 50%

Keyphrases

• Orientation Optimization 100%
• Channel Orientation 25%
• Design Layout 25%
• Process Physics 25%
• Gating Model 25%