Low-power FinFET circuit synthesis using surface orientation optimization

Prateek Mishra, Niraj K. Jha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

25 Scopus citations


FinFETs with channel surface along the 〈110〉 plane can be easily fabricated by rotating the fins by 45° from the plane. By designing logic gates, which have pFinFETs in the 〈110〉 plane and nFinFETs in the 〈100〉 plane, the gate delay can be reduced by as much as 14%, compared to the conventional 〈100〉 logic gates. The reduction in delay can be traded off for reduced power in FinFET circuits. In this paper, we propose a low-power FinFET-based circuit synthesis methodology based on surface orientation optimization. We study various logic design styles, which depend on different FinFET channel orientations, for synthesizing low-power circuits. We use BSIM, a process/physics based double-gate model in HSPICE, to derive accurate delay and power estimates. We design layouts of standard library cells containing FinFETs in different orientations to obtain an accurate area estimate for the low-power synthesized netlists after place-and-route. We use a linear programming based optimization methodology that gives power-optimized netlists, consisting of oriented gates, at tight delay constraints. Experimental results demonstrate the efficacy of our scheme.

Original languageEnglish (US)
Title of host publicationDATE 10 - Design, Automation and Test in Europe
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages4
ISBN (Print)9783981080162
StatePublished - 2010
EventDesign, Automation and Test in Europe Conference and Exhibition, DATE 2010 - Dresden, Germany
Duration: Mar 8 2010Mar 12 2010

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
ISSN (Print)1530-1591


OtherDesign, Automation and Test in Europe Conference and Exhibition, DATE 2010

All Science Journal Classification (ASJC) codes

  • General Engineering


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