TY - GEN
T1 - Low power distributed embedded systems
T2 - 9th International Conference on High Performance Computing, HiPC 2002
AU - Luo, Jiong
AU - Jha, Niraj K.
N1 - Publisher Copyright:
© Springer-Verlag Berlin Heidelberg 2002.
PY - 2002
Y1 - 2002
N2 - In this paper, we survey multi-objective system synthesis algorithms for lowp ower real-time systems-on-a-chip (SOCs), distributed and wireless client-server embedded systems, distributed embedded systems with reconfigurable field-programmable gate arrays (FPGAs), as well as distributed systems of SOCs. Many of these synthesis algorithms target simultaneous optimization of different cost objectives, including system price, area and power consumption. Dynamic voltage scaling has proved to be a powerful technique for reducing power consumption. We also survey several dynamic voltage scaling techniques for distributed embedded systems containing voltage-scalable processors. The dynamic voltage scaling algorithms can be embedded in the inner-loop of a system synthesis framework and provide feedback for system-level design space exploration. Besides voltage-scalable processors, dynamically voltagescalable links have also been proposed for implementing high performance and low power interconnection networks for distributed systems. We survey relevant techniques in this area as well.
AB - In this paper, we survey multi-objective system synthesis algorithms for lowp ower real-time systems-on-a-chip (SOCs), distributed and wireless client-server embedded systems, distributed embedded systems with reconfigurable field-programmable gate arrays (FPGAs), as well as distributed systems of SOCs. Many of these synthesis algorithms target simultaneous optimization of different cost objectives, including system price, area and power consumption. Dynamic voltage scaling has proved to be a powerful technique for reducing power consumption. We also survey several dynamic voltage scaling techniques for distributed embedded systems containing voltage-scalable processors. The dynamic voltage scaling algorithms can be embedded in the inner-loop of a system synthesis framework and provide feedback for system-level design space exploration. Besides voltage-scalable processors, dynamically voltagescalable links have also been proposed for implementing high performance and low power interconnection networks for distributed systems. We survey relevant techniques in this area as well.
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U2 - 10.1007/3-540-36265-7_63
DO - 10.1007/3-540-36265-7_63
M3 - Conference contribution
AN - SCOPUS:84945281660
SN - 3540003037
SN - 9783540003038
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 679
EP - 693
BT - High Performance Computing - HiPC 2002 - 9th International Conference, Proceedings
A2 - Sahni, Sartaj
A2 - Prasanna, Viktor K.
A2 - Shukla, Uday
PB - Springer Verlag
Y2 - 18 December 2002 through 21 December 2002
ER -