Abstract
The need to reduce the power consumption of the next generation of digital systems is clearly recognized. There are significant research efforts along multiple fronts directed towards this end. This includes designing devices that operate on lower voltages, designing innovative circuits which have reduced power consumption, selecting logic designs which have lower power consumption, and smart power management techniques at the system level which shut off large portions of the system when they are not being used. This paper surveys a range of power optimization techniques used at different levels of design abstraction. Special emphasis has been placed on techniques that have been successfully integrated into industrial practice.
| Original language | English (US) |
|---|---|
| Title of host publication | IEEE Region 10 Annual International Conference, Proceedings/TENCON |
| Publisher | IEEE |
| Pages | 118-123 |
| Number of pages | 6 |
| Volume | 1 |
| ISBN (Print) | 0780348869 |
| State | Published - Dec 1 1999 |
| Externally published | Yes |
| Event | Proceedings of the 1998 IEEE Region 10 International Conference on 'Global Connectivity in Energy, Computer, Communication and Control (TENCON '98) - New Delhi, India Duration: Dec 17 1998 → Dec 19 1998 |
Other
| Other | Proceedings of the 1998 IEEE Region 10 International Conference on 'Global Connectivity in Energy, Computer, Communication and Control (TENCON '98) |
|---|---|
| City | New Delhi, India |
| Period | 12/17/98 → 12/19/98 |
All Science Journal Classification (ASJC) codes
- Engineering(all)
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Cite this
Mehra, R., & Malik, S. (1999). Low power digital system design: an overview. In IEEE Region 10 Annual International Conference, Proceedings/TENCON (Vol. 1, pp. 118-123). IEEE.