For all technologies, from flint arrowheads to DNA microarrays, patterning the functional material is crucial. For semiconductor integrated circuits (ICs), it is even more critical than for most technologies because enormous benefits accrue to going smaller, notably higher speed and much less energy consumed per computing function. The consensus is that ICs will continue to be manufactured until at least the ldquo22 nm noderdquo (the linewidth of an equal line-space pattern). Most patterning of ICs takes place on the wafer in two steps: (a) lithography, the patterning of a resist film on top of the functional material; and (b) transferring the resist pattern into the functional material, usually by etching. Here we concentrate on lithography. Optics has continued to be the chosen lithographic route despite its continually forecast demise. A combination of 193-nm radiation, immersion optics, and computer-intensive resolution enhancement technology will probably be used for the 45- and 32-nm nodes. Optical lithography usually requires that we first make a mask and then project the mask pattern onto a resist-coated wafer. Making a qualified mask, although originally dismissed as a ldquosupport technology,rdquo now represents a significant fraction of the total cost of patterning an IC largely because of the measures needed to push resolution so far beyond the normal limit of optical resolution. Thus, although optics has demonstrated features well below 22 nm, it is not clear that optics will be the most economical in this range; nanometer-scale mechanical printing is a strong contender, extreme ultraviolet is still the official front runner, and electron beam lithography, which has demonstrated minimum features less than 10 nm wide, continues to be developed both for mask making and for directly writing on the wafer (also known as ldquomaskless lithographyrdquo). Going from laboratory demonstration to manufacturing technology is enormously expensive ( $1 billion) and for good reason. Just in terms of data rate (mask pattern to resist pattern), today's exposure tools achieve about 10 Tb/s at an allowable error rate of about 1/h; this data rate will double with each generation. In addition, the edge placement precision required will soon be 30 parts per billion. There are so many opportunities for unacceptable performance that making the right decision goes far beyond understanding the underlying physical principles. But the benefits of continuing to be able to manufacture electronics at the 22-nm node and beyond appear to justify the investment, and there is no shortage of ideas on how to accomplish this.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
- Electron beam lithography
- Imprint lithography
- Ion beam lithography
- Laser beam lithography
- Phase separation