## Abstract

This paper addresses problems that arise while checking the equivalence of two Boolean functions under arbitrary input permutations. The permutation problem has several applications in the synthesis and verification of combinational logic: it arises in the technology mapping stage of logic synthesis and in logic verification. A popular method to solve it is to compute a signature for each variable that helps to establish a correspondence between the variables. Several researchers have suggested a wide range of signatures that have been used for this purpose. However, for each choice of signature, three remain variable that cannot be uniquely identified. Our research has shown that, for a given example, this set of problematic variables tends to be the same - regardless of the choice of signatures. The paper investigates this problem.

Original language | English (US) |
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Pages (from-to) | 167-191 |

Number of pages | 25 |

Journal | Formal Methods in System Design |

Volume | 21 |

Issue number | 2 |

DOIs | |

State | Published - Sep 2002 |

## All Science Journal Classification (ASJC) codes

- Software
- Theoretical Computer Science
- Hardware and Architecture

## Keywords

- High level design tools
- Permutation independent Boolean comparison
- Reduced ordered binary decision diagram
- Synthesis and verification