Limits and graph structure of available instruction-level parallelism

Darko Stefanović, Margaret Martonosi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Scopus citations

Abstract

We reexamine the limits of parallelism available in programs, using run-time reconstruction of program data-flow graphs. While limits of parallelism have been examined in the context of superscalar and VLIW machines, we also wish to study the causes of observed parallelism by examining the structure of the reconstructed data-flow graph. One aspect of structure analysis that we focus on is the isolation of instructions involved only in address calculations. We examine how address calculations present in RISC instruction streams generated by optimizing compilers affect the shape of the data-flow graph and often significantly reduce available parallelism.

Original languageEnglish (US)
Title of host publicationEuro-Par 2000 Parallel Processing - 6th International Euro-Par Conference, Proceedings
EditorsArndt Bode, Thomas Ludwig, Wolfgang Karl, Roland Wismüller
PublisherSpringer Verlag
Pages1018-1022
Number of pages5
ISBN (Electronic)9783540679561
DOIs
StatePublished - 2000
Event6th International European Conference on Parallel Computing, Euro-Par 2000 - Munich, Germany
Duration: Aug 29 2000Sep 1 2000

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume1900
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Other

Other6th International European Conference on Parallel Computing, Euro-Par 2000
CountryGermany
CityMunich
Period8/29/009/1/00

All Science Journal Classification (ASJC) codes

  • Theoretical Computer Science
  • Computer Science(all)

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