Leakage power analysis and reduction during behavioral synthesis

This paper presents a high-level leakage power analysis and reduction algorithm. The algorithm uses device level models for leakage to pre-characterize a given register transfer level module library. This is used to estimate the power consumption of a circuit due to leakage. The algorithm can also identify and extract the frequently idle modules in the datapath, which may be targeted for low-leakage optimization. Leakage optimization is based on the use of dual threshold voltage (V_T) technology. The algorithm prioritizes modules giving a high-level synthesis (HLS) system an indication of where most gains for leakage reduction may be found. Results show that using a dual-V_T library during HLS can reduce leakage power by an average of 59% for the different technology generations. Total power can be reduced by an average of 18.8% to 45.4% for 0.18 μm to 0.07 μm technologies, respectively, compared to register-transfer level (RTL) circuits optimized for switching power only. The contribution of leakage power to overall power consumption of switching power optimized RTL circuits ranges from 23.5% to 54.1%. Our approach reduced these values to 11.4% to 25.9%.