Leakage Current Modeling of Series-Connected Thin Film Transistors

J. C. Sturm; I. W. Wu; M. Hack

doi:10.1109/16.398673

Leakage Current Modeling of Series-Connected Thin Film Transistors

J. C. Sturm, I. W. Wu, M. Hack

Research output: Contribution to journal › Article › peer-review

5 Scopus citations

Abstract

The leakage current of an arbitrary number of series-connected polysilicon Thin Film Transistors (TFT's) with a common gate is shown to be easily computed from the I-V characteristics of a single FET for the first time, both by an analytical model and by graphical techniques. Good agreement with experimental data is obtained for drain biases greater than ~1 V. The work is also applicable to single crystal Silicon-On-Insulator (SOI) TFT's.

Original language	English (US)
Pages (from-to)	1561-1563
Number of pages	3
Journal	IEEE Transactions on Electron Devices
Volume	42
Issue number	8
DOIs	https://doi.org/10.1109/16.398673
State	Published - Aug 1995

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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title = "Leakage Current Modeling of Series-Connected Thin Film Transistors",

abstract = "The leakage current of an arbitrary number of series-connected polysilicon Thin Film Transistors (TFT's) with a common gate is shown to be easily computed from the I-V characteristics of a single FET for the first time, both by an analytical model and by graphical techniques. Good agreement with experimental data is obtained for drain biases greater than ~1 V. The work is also applicable to single crystal Silicon-On-Insulator (SOI) TFT's.",

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