@article{3e26b5ed739f4f47a8894bf4bb5d39d9,
title = "Leakage Current Modeling of Series-Connected Thin Film Transistors",
abstract = "The leakage current of an arbitrary number of series-connected polysilicon Thin Film Transistors (TFT's) with a common gate is shown to be easily computed from the I-V characteristics of a single FET for the first time, both by an analytical model and by graphical techniques. Good agreement with experimental data is obtained for drain biases greater than ~1 V. The work is also applicable to single crystal Silicon-On-Insulator (SOI) TFT's.",
author = "Sturm, {J. C.} and Wu, {I. W.} and M. Hack",
note = "Funding Information: 11. OVERVIEW AND GRAPHICAL ANALYSIS When two transistors are connected in series (Fig. l(a.)) their drain currents must be equal, assuming no gate leakage. Therefore the voltage on the intermediate terminal, labeled vD,l , must adjust itself to this condition. When the gate voltage of a typical polysilicon NMOS TFT is below some nominal value, e.g., -2 V in Fig. 2, the leakage current rises as the gate-source voltage becomes more negative. This is due to high-electric field tunneling at specific trap sites near the high-field drain region [6]-[8], resulting in a channel current dominated by holes. Also, the leakage current in this regime increases strongly as the drain voltage is increased, The top transistor will have its source at a higher voltage than the lower one, and hence have a more negative VGS than the lower transistor. Therefore the applied VDDw ill divide itself so that most of the applied voltage falls across the lower transistor, giving it a larger VDS so that the Manuscript received November 30, 1994; revised March 17, 1995. The review of this brief was arranged by Associate Editor W. F. Kosonocky. The work at Princeton was supported by DARF{\textquoteright}A through Grant USAF-TPSU-CCT-1464-966 and by Hitachi. J. C. Sturm is with the Department of Electrical Engineering and the Photonic and Opto-Electronic Materials Center (POEM), Princeton University, Princeton, NJ 08544 USA. 1.-W. Wu and M. Hack are with the Xerox Palo Alto Research Center, Palo Alto, CA 94304 USA. IEEE Log Number 9412376.",
year = "1995",
month = aug,
doi = "10.1109/16.398673",
language = "English (US)",
volume = "42",
pages = "1561--1563",
journal = "IEEE Transactions on Electron Devices",
issn = "0018-9383",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "8",
}