The semiconductor industry has showcased a spectacular exponential growth in the number of transistors per integrated circuit for several decades, as predicted by Moore's law. Figure 1 shows the future technology trend predicted by ITRS (International Technology Roadmap for Semiconductors) . By 2023, the physical gate length would scale down to 4.5 nm. Actually, according to a study , future devices could theoretically scale down to 1.5 nm with 0.04 ps switching speed and 0.017 eV energy consumption. However, maintaining such an exponential growth rate is a major challenge. Physical dimensions and electrostatic limitations faced by conventional process and fabrication technologies will likely thwart the dimensional scaling of complementary metal-oxide-semiconductor (CMOS) devices within the next decade. Figure 2 from ITRS shows that after 2016, the manufacturable solutions are unknown (the shaded area).
|Original language||English (US)|
|Title of host publication||Nanoelectronic Circuit Design|
|Publisher||Springer New York|
|Number of pages||22|
|State||Published - 2011|
All Science Journal Classification (ASJC) codes