Interconnect-aware low-power high-level synthesis

Computer Science

• High Level Synthesis 100%
• Power Consumption 66%
• Power Optimization 33%
• Level Architecture 33%
• Register-Transfer Level 33%
• Datapath 33%
• Clock Distribution Networks 33%
• Switching Activity 33%
• Multiplexer 33%
• Design Information 33%
• Physical Design 33%
• Coupling Capacitance 33%

Keyphrases

• Design Coupling 25%
• Capacitance Reduction 25%