Interconnect-aware high-level synthesis for low power

Keyphrases

• High-level Synthesis 100%
• Synthesis for Low Power 100%
• Interconnect Power 100%
• Area Overhead 50%
• Overall Power 50%
• Power Reduction 50%
• Power Optimization 25%
• Multiplexer 25%
• Register Transfer Level 25%
• Area Optimized 25%
• Power Consumption 25%
• Power Optimized 25%
• Design Information 25%
• On-chip Interconnects 25%
• Deep Submicron Technology 25%
• Inter-wire Coupling 25%
• Clock Distribution Network 25%
• Switching Activity 25%
• Circuit Power 25%
• Interconnect Wire 25%
• Coupling Capacitance 25%
• Power Consumption Reduction 25%
• Physical Design 25%

Computer Science

• High Level Synthesis 100%
• Experimental Result 33%
• Power Optimization 33%
• Level Architecture 33%
• Functional Unit 33%
• Power Consumption 33%
• Register-Transfer Level 33%
• Clock Distribution Networks 33%
• Reduce Power Consumption 33%
• Switching Activity 33%
• Multiplexer 33%
• Design Information 33%
• Physical Design 33%