Integration of hierarchical test generation with behavioral synthesis of controller and data path circuits

Sandeep Bhatia, Niraj K. Jha

Research output: Contribution to journalArticle

23 Scopus citations

Abstract

This paper describes the first behavioral synthesis system that incorporates a hierarchical test generation approach to synthesize area-efficient and highly testable controller/data path circuits. Functional information of circuit modules is used during the synthesis process to facilitate complete and easy testability of the data path. The controller behavior is taken into account while targeting data path testability. No direct controllability of the controller outputs through scan or otherwise is assumed. The test set for the combined controller/data path is generated during synthesis in a very short time. Near 100% testability of combined controller and data path is achieved. The synthesis system easily handles large bit-width data path circuits with sequential loops and conditional branches in their behavioral specification, and scheduling constructs like multicycling, chaining and structural pipelining. An improvement of about three to four orders of magnitude was usually obtained in the test generation time for the synthesized benchmarks as compared to an efficient gate-level sequential test generator. The testability overheads are almost zero. Furthermore, in many cases at-speed testing is also possible.

Original languageEnglish (US)
Pages (from-to)608-619
Number of pages12
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume6
Issue number4
DOIs
StatePublished - Dec 1 1998

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Keywords

  • Controller/data path testing
  • Hierarchical testability
  • High-level synthesis
  • Synthesis for testability

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