Integration of butterfly and inverse butterfly nets in embedded processors: Effects on power saving

G. C. Cardarilli, L. Di Nunzio, R. Fazzolari, M. Re, Ruby B. Lee

Research output: Chapter in Book/Report/Conference proceedingConference contribution

18 Scopus citations

Abstract

Many software functions are not efficiently executed by standard microprocessors. This happens when the operation granularity and data wordlength are different with respect to those of the microprocessor's architecture. Important improvements in speed and power can be obtained by integrating hardware accelerators in standard microprocessor architectures. This work, based on [1], shows that the integration of a Bit Manipulation Unit (BMU) [2] in an Altera NIOS-2 soft processor architecture [3] allows very interesting speed-up and power saving factors.

Original languageEnglish (US)
Title of host publicationConference Record of the 46th Asilomar Conference on Signals, Systems and Computers, ASILOMAR 2012
Pages1457-1459
Number of pages3
DOIs
StatePublished - Dec 1 2012
Event46th Asilomar Conference on Signals, Systems and Computers, ASILOMAR 2012 - Pacific Grove, CA, United States
Duration: Nov 4 2012Nov 7 2012

Publication series

NameConference Record - Asilomar Conference on Signals, Systems and Computers
ISSN (Print)1058-6393

Other

Other46th Asilomar Conference on Signals, Systems and Computers, ASILOMAR 2012
CountryUnited States
CityPacific Grove, CA
Period11/4/1211/7/12

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Computer Networks and Communications

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