TY - GEN
T1 - Integration of butterfly and inverse butterfly nets in embedded processors
T2 - 46th Asilomar Conference on Signals, Systems and Computers, ASILOMAR 2012
AU - Cardarilli, G. C.
AU - Di Nunzio, L.
AU - Fazzolari, R.
AU - Re, M.
AU - Lee, Ruby B.
N1 - Copyright:
Copyright 2013 Elsevier B.V., All rights reserved.
PY - 2012
Y1 - 2012
N2 - Many software functions are not efficiently executed by standard microprocessors. This happens when the operation granularity and data wordlength are different with respect to those of the microprocessor's architecture. Important improvements in speed and power can be obtained by integrating hardware accelerators in standard microprocessor architectures. This work, based on [1], shows that the integration of a Bit Manipulation Unit (BMU) [2] in an Altera NIOS-2 soft processor architecture [3] allows very interesting speed-up and power saving factors.
AB - Many software functions are not efficiently executed by standard microprocessors. This happens when the operation granularity and data wordlength are different with respect to those of the microprocessor's architecture. Important improvements in speed and power can be obtained by integrating hardware accelerators in standard microprocessor architectures. This work, based on [1], shows that the integration of a Bit Manipulation Unit (BMU) [2] in an Altera NIOS-2 soft processor architecture [3] allows very interesting speed-up and power saving factors.
UR - http://www.scopus.com/inward/record.url?scp=84876206961&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84876206961&partnerID=8YFLogxK
U2 - 10.1109/ACSSC.2012.6489268
DO - 10.1109/ACSSC.2012.6489268
M3 - Conference contribution
AN - SCOPUS:84876206961
SN - 9781467350518
T3 - Conference Record - Asilomar Conference on Signals, Systems and Computers
SP - 1457
EP - 1459
BT - Conference Record of the 46th Asilomar Conference on Signals, Systems and Computers, ASILOMAR 2012
Y2 - 4 November 2012 through 7 November 2012
ER -